The following error occurs when imx8mm is used for SN65DSI86, Linux5.10
ti_sn65dsi86 3-002d: [drm:ti_sn_bridge_enable] *ERROR* Link training failed, link is off (-5)
This is my schematic design
I saw on another post that ASSR needs to be turned off
Is there a new driver?
Thank you very much for your reply. Now the chip register value I read is as follows. Could you help me analyze the cause of the error
In ASSR mode, I design that the TEST2 pin is connected to GND on the hardware. Can we turn off ASSR mode without modifying the hardware
Can we turn off ASSR mode without modifying the hardware
You need TEST2 to be pulled up to change ASSR as it is read only mode if it is pulled down.
You have bits set in registers 0xF4, 0xF5, and 0xF8. Here is the description from the datasheet
It seems there is a pll unlock. This means that you have an incorrect register settings for the device. Please use the register calculator found in this thread. https://e2e.ti.com/support/interface-group/interface/f/interface-forum/945404/faq-sn65dsi86-how-do-i-programming-the-sn65dsi86-registers?tisearch=e2e-sitesearch&keymatch=sn65dsi86#
Sorry, I still can't train successfully
1. I still cannot calculate the value that the register should be set to from this execl
My screen information is as follows. How do I know how to operate the EDID Formatting Space? Can you guide me? Thank you very much.
20190416110313019_TFT-LCD Approval Specification N156HCA-EAB_for Lenovo_LBG_C1 ver3.0_20180116.pdf
2. In terms of hardware, can I just set TEST2 to 1.8V?
3. For reference clock, would it be simpler to use an external crystal oscillator?
This solved my problem. I attached a 27M external crystal oscillator, pulled up TEST2, and set the register. It works normally. Thank you for your support.
