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DS90UB941AS-Q1EVM: Split DOUT Channel not working with EVM - We are trying to use pattern in two display

caio yoshino
Prodigy 20 points
Part Number: DS90UB941AS-Q1EVM

Hello, we are trying to use two display using the split function from DS90UB941AS-Q1EVM.

Before start using DSI input, we are trying to use the pattern generator from EVM. 

We are trying the tests bellow.

- 1 four HSD vias and 1 DIsplay - > Pattern generator works.

- 1 cable Y - 2 lanes  DSOUT 1 and DOUT 2 and 2 display - > Pattern Generator NOT functional 

- 1 cable Y - 2 lanes  DSOUT 1 and DOUT 2 and 1 display - > Pattern Generator NOT functional 

We don´t have the schematic from Display. We just know that have DS90UB948 Deserializer. And receive two channels from DSOUT.

Could you please help us, if you have another test for use two displays with this configurations?

  • 0
    TI__Genius 10895 points

    Hi Caio,

    Thanks for your question! I can help you with the DS90UB941AS configuration to generate split images for PATGEN to two displays.

    I'll ask a few questions to better understand and verify the end-to-end setup between the serializer-deserializer devices.

    > Do you mind sharing a more detailed version of your configuration from the Y-HSD cable? Specifically, how it transfers from the 941AS to the HSD input of the 948 board (pin to pin connections)

    > A schematic would also be helpful here to do an in-depth analysis of hardware and strap connections.

    > Do you have an initialization script that can be shared for the 941AS?

    Best,

    Miguel

  • 0 in reply to caio yoshino
    TI__Genius 10895 points

    Hi Caio,

    Thank you for sharing the serializer schematic and cabling choice!

    I have a few questions about the serializer schematic to start;

    1) For the L1 and L2 common-mode chokes, it appears that the pins 1 and 4, 2 and 3 are shorted. Is this intentional for the use of the device?

    2) For the cable provided, it appears that the DOUT0 P/N and DOUT1 P/N connections route to different connectors. I would imagine if the routing is the same as above, the DOUT0 P/N and DOUT1 P/N signals would route to the same single connector, then split to the two other connectors with alternating pin configurations.

    Would you mind sharing the deserializer portions of the schematic as well?

    If you have concerns about sharing further schematics and design details, feel free to also reach out to me via m-bolante@ti.com or in the direct message feature of E2E!

    Best,

    Miguel

  • 0 in reply to Miguel Bolante
    Prodigy 20 points

    Hi Miguel, follow the answers bellow.

    1-) About L1 and L2 we keep as the same as EVM, just a place holder if need. 

    2-) The cable, that I have shared is for EVM kit that have one conector and we split the cable, for the schematic that I have shared is for the product solution, that we need to split DOUT with 2 cables (The cables are four pin HSD).

    3-) For Deserializer I don´t Have the schematic, is a third part. That have one input for four pin HSD connector with DS90UB948 Deserializer. 

  • 0 in reply to caio yoshino
    TI__Genius 10895 points

    Hi Caio,

    Thanks for providing!

    Taking a step back, can we try running the scripting configuration from the EVM to see if this generates a pattern on the displays?

    I am assuming the resolutions of the displays are 1920 x 720p, but correct me if this is not the case:

    import time

# timing for each panel is 1920*720@60
# Total Horizontal = '2070'
# uVisWidth        = '1920'
# uHsyncFrontPorch = '50'
# uHsyncWidth      = '50'
# uHsyncBackPorch  = '50'
# Total Vertical   = '870'
# uVisHeight       = '720'
# uVsyncFrontPorch = '50'
# uVsyncWidth      = '50'
# uVsyncBackPorch  = '50'
# uPixelFreqInHz   = '108054000'


Ser_addr = 0x18

time.sleep(0.5)
board.WriteI2C(Ser_addr,0x01,0x08) # Reset
board.WriteI2C(Ser_addr,0x01,0x02) # Reset



time.sleep(0.5)
board.WriteI2C(Ser_addr,0x5B,0x07) #Set 941AS to Splitter mode

board.WriteI2C(Ser_addr,0x1E,0x01) #Select FPD-Link III Port 0
board.WriteI2C(Ser_addr,0x66,0x1A)
board.WriteI2C(Ser_addr,0x67,0x01) #M=1
board.WriteI2C(Ser_addr,0x66,0x03)
board.WriteI2C(Ser_addr,0x67,0x02) #N=2

board.WriteI2C(Ser_addr,0x66,0x04)
board.WriteI2C(Ser_addr,0x67,0x16) #least 8 bit of Total Horizontal frame size
board.WriteI2C(Ser_addr,0x66,0x05)
board.WriteI2C(Ser_addr,0x67,0x68) #Least 4 bit TV + Most 4 bit TH
board.WriteI2C(Ser_addr,0x66,0x06)
board.WriteI2C(Ser_addr,0x67,0x36) #Most 8 bit of Total Vertical frame size

board.WriteI2C(Ser_addr,0x66,0x07)
board.WriteI2C(Ser_addr,0x67,0x80) #least 8 bit of active Horizontal frame size
board.WriteI2C(Ser_addr,0x66,0x08)
board.WriteI2C(Ser_addr,0x67,0x07) #Least 4 bit AV + Most 4 bit AH
board.WriteI2C(Ser_addr,0x66,0x09)
board.WriteI2C(Ser_addr,0x67,0x2D) #Most 8 bit of active Vertical frame size

board.WriteI2C(Ser_addr,0x66,0x0A)
board.WriteI2C(Ser_addr,0x67,0x32) #Horizontal Sync Width
board.WriteI2C(Ser_addr,0x66,0x0B)
board.WriteI2C(Ser_addr,0x67,0x32) #Vertical Sync Width
board.WriteI2C(Ser_addr,0x66,0x0C)
board.WriteI2C(Ser_addr,0x67,0x32) #Horizontal back porch
board.WriteI2C(Ser_addr,0x66,0x0D)
board.WriteI2C(Ser_addr,0x67,0x32) #Vertical back porch
board.WriteI2C(Ser_addr,0x65,0x04) #using internal timing and internal clock
board.WriteI2C(Ser_addr,0x64,0x15) #enable PG/color bars

board.WriteI2C(Ser_addr,0x1E,0x02) #Select FPD-Link III Port 0
board.WriteI2C(Ser_addr,0x66,0x1A)
board.WriteI2C(Ser_addr,0x67,0x01) #M=1
board.WriteI2C(Ser_addr,0x66,0x03)
board.WriteI2C(Ser_addr,0x67,0x02) #N=2

board.WriteI2C(Ser_addr,0x66,0x04)
board.WriteI2C(Ser_addr,0x67,0x16) #least 8 bit of Total Horizontal frame size
board.WriteI2C(Ser_addr,0x66,0x05)
board.WriteI2C(Ser_addr,0x67,0x68) #Least 4 bit TV + Most 4 bit TH
board.WriteI2C(Ser_addr,0x66,0x06)
board.WriteI2C(Ser_addr,0x67,0x36) #Most 8 bit of Total Vertical frame size

board.WriteI2C(Ser_addr,0x66,0x07)
board.WriteI2C(Ser_addr,0x67,0x80) #least 8 bit of active Horizontal frame size
board.WriteI2C(Ser_addr,0x66,0x08)
board.WriteI2C(Ser_addr,0x67,0x07) #Least 4 bit AV + Most 4 bit AH
board.WriteI2C(Ser_addr,0x66,0x09)
board.WriteI2C(Ser_addr,0x67,0x2D) #Most 8 bit of active Vertical frame size

board.WriteI2C(Ser_addr,0x66,0x0A)
board.WriteI2C(Ser_addr,0x67,0x32) #Horizontal Sync Width
board.WriteI2C(Ser_addr,0x66,0x0B)
board.WriteI2C(Ser_addr,0x67,0x32) #Vertical Sync Width
board.WriteI2C(Ser_addr,0x66,0x0C)
board.WriteI2C(Ser_addr,0x67,0x32) #Horizontal back porch
board.WriteI2C(Ser_addr,0x66,0x0D)
board.WriteI2C(Ser_addr,0x67,0x32) #Vertical back porch
board.WriteI2C(Ser_addr,0x65,0x04) #using internal timing and internal clock
board.WriteI2C(Ser_addr,0x64,0x31) #enable PG/color bars

#0x01,0x00, #enable DSI

board.WriteI2C(Ser_addr,0x1E,0x01) #Select FPD-Link III Port 0
board.WriteI2C(Ser_addr,0x07,0x58) #0x07,0x58
board.WriteI2C(Ser_addr,0x08,0x5C) #0x08,0x5c
board.WriteI2C(Ser_addr,0x03,0x9A) #0x03,0x9A Enable I2C_PASSTHROUGH, FPD-Link III Port 0


board.WriteI2C(Ser_addr,0x1E,0x02) #Select FPD-Link III Port 1 0x1E,0x02, 
board.WriteI2C(Ser_addr,0x07,0x58) #0x07,0x58
board.WriteI2C(Ser_addr,0x08,0x5E) #0x08,0x5E
board.WriteI2C(Ser_addr,0x03,0x9A) #0x03,0x9A Enable I2C_PASSTHROUGH, FPD-Link III Port 1
board.WriteI2C(Ser_addr,0x1E,0x04) #0x1E,0x04

    If this script still proves to be unsuccessful, we may have to explore the configuration of the HSD pins further from the Y-Split cable. Please let me know the results of testing.

    Best,

    Miguel