DS90UB941AS-Q1EVM: MIPI DSI CONFIG with Qualcomm SOC

DATA

CLK

NO ERRORS IN LANE. But no video.

Hi Caio,

Just want to confirm first, did PatGen with internal timing, internal clock output video (1) ? If so, did PatGen with internal timing and external clock also work (2)?

What deserializer are you pairing this with? Did the pattern generation on the previous steps display as expected? On the current step (3), what output are you seeing on the display? 



Best regards,
Ikram

1 - Timing source = Internal -> Pattern OK -> Collor Bar in the Display -OK

2 - Timing Source = Internal w/ Ext  CLK -> Pattern OK -> Collor Bar in the Display  - OK

3 - Timing Source = External -> Not  OK -> Black Screen in the Display - NOK

We are using a DS90UB948 Deserializer with LVDS Display. The Pattern Display are displayed as expected. We have no video. Just the black screen in step 3. 

In step 3, you have the PatGen enabled correct? Could you also disable PatGen and try end-to-end video? 

Could you also please check if there is lock loss on the DES and the SER 0xC register status.

In step 3, you have the PatGen enabled correct?
Yes
Could you also disable PatGen and try end-to-end video?

We already turn off the enable the dsi, but didn't see any video. Did we need some some sequence configuration to start the video?

Could you also please check if there is lock loss on the DES and the SER 0xC register status.
I'm out of office now, but we are using the Texas GUI, and in the status it is showing that the deserialyzer is connected.

Hi Caio, please still read registers to check for any errors. 

caio yoshino said:

Did we need some some sequence configuration to start the video?

If you turn off the "Enable Generator", that should disable PatGen and pass through the DSI video.

Hi Ikran, follow the register read. 

,

Hi Caio,

Could you please get all the registers using the save button from the Register tab on ALP. Then we can narrow down what is causing the DSI_ERROR. It would also help to check if the mode selections are correct.

Also, could you check if your initialization sequence matches that described in section 10.2. The init. sequence shows how you can disable DSI input temporarily, then set the DSI modes and clock settings.

Best regards,
Ikram

1614.Register_Dump.zip

Hi Ikram,

Attached is dump file.

We followed the 10.2 initialization sequence, but when we apply the step "Register 0x42 = 0x0A" the register value return to 0x00. Is it Right?

Hi Caio, Yes, the 0x42 register is used to write to the indirect registers. Please give me till Tuesday to look into this and get back to you.

Best regards,
Ikram

Hi Ikran , thanks, we will wait for your reply. 

Another question, we received from Qualcomm Soc team a request. If are possible to verify how many valid MIPI DSI package are received from Serializer, just to confirm if the SOC side is ok?

Hi Caio,

To confirm DSI input they can check the "DSI_ERROR_DET" bit in the General Status register and "DSI_STATUS" register, mentioned in the "DSI Error Reporting" section.

There is also a DSI Error Counter that can be configured as described in the datasheet. 

Best regards,
Ikram

Hi Ikram, thanks for your reply. We can get the DSI report. 
About the dump register analysis do you have an update? Did you find some information? 

Hi Ikran,

Follow our DSI config, could you please check if some parameters are wrong? 

We still don´t have image in the display.

Hi Caio,

It seems that there are CRC back channel errors, as indicated on register 0xC and 0xA counter.
And register 0xC shows that there are flags for DPHY_ERROR, DSI_ERROR and DES_ERROR.

Just to confirm, is your system running continuous DSI clock? Also, is it 4 lane, single-DSI mode and connected to port 0?

It seems that the issue is with the DSI input, since SER PatGen was working. From the SoC side could you tell us what the total resolution and target PCLK is?

Best regards,
Ikram

Thank you Caio. Please let us know if you have any further questions.

Best regards,
Ikram