DP83822I: register setting timing during power-up

Hi Go,

Are you referring to the following foot note:

AVD ramping up after VDDIO ramp completion is preferred to avoid false detection of lower level of VDDIO in any corner case.

1. After power the PHY is done powering up, the registers are set. Usually takes ~200ms for registers to be ready for access. 

2. MDIO communication only requires a 2.5 kΩ PU resistor on the MDIO line, MDC does not require any PU/PD resistors.

Regards,

Alvaro

Hi, Alvaro

Thank you for your comment.

Regarding your comment,

・the ”～200ms” means T2 on Figure7.1, is it correct?

・In the D/S, MDIO line requires 2.2kΩ PU resistor. which is correct?

Thanks,

Go 

Hi, Alvaro

Thank you for your comment.

Regarding my question on this thread below , there was a typo.

２．Are there other registers related to MDIO communication which is set during Figure 7-1. Power-Up Timing?

 I'm sorry for the confusion this has caused...(I didn't mean resistor)

I really appreciate if you could give me some comment for that.

Thanks,

Go

Hi Go,

All Registers are set once the PHY is powered on, they cannot be accessed until 200ms after power up. Am I understanding your question correctly?

Regards,

Alvaro

Hi, Alvaro

Thank you for your comment.

I'm really sorry to trouble you , but just one more thing I'd like to ask.

Does DP83822I set the bit 1:0 of Register 0x421 by detecting the voltage at VDDIO pin directly? 

Thanks,

Go

Hi Go,

This is internal information. Is there any functional issues you are experiencing?

Regards,

Alvaro

Hi, Alvaro

I'm really sorry for my late reply.

Does "internal information" mean that it's confidential?