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Original question:

TCAN1146-Q1: Global Fault Flag work principle

TCAN1146-Q1: the time difference between the failing edge of SPI CLK to the rising edge of nCS

Wenting Wu
Intellectual 2190 points
Part Number: TCAN1146-Q1

Hello expert,

May I ask must the time difference (TCSH) between the failing edge of SPI CLK to the rising edge of nCS be kept in 100ns?

My customer uses F28P65(C2000)'s SPI to communicate with TCAN1146-Q1, while its the time difference SPICLK to nCS is just 3ns. My customer doesn't meet the communication issue now. However, we still check if there are any risks?

Best regards,

wenting 

  • 0
    TI__Guru 51025 points

    Hi Wenting,

    The TCAN1146 will count the number of SCK cycles that occur within one assertion of the nCS pin. A SPI write will only be accepted if a multiple of 8 bits is received during this time. With such a short timing between the last clock cycle and the deassertion of the nCS pin, there is a risk that the transceiver will not count the last bit and the SPI write will be thrown out (this would also cause the SPIERR flag to be set so the failure would be indicated to the MCU). 

    I would recommend that the customer add some extra delay in the transaction so that the 100ns disable time is met. This will ensure that the transceiver counts the correct number of bits during the transaction period and the SPI write is accepted. 

    Let me know if you have any more questions. 

    Regards, 
    Eric Schott