TCAN1145-Q1: TCAN1145-Q1 pin define issue

Hi Lawrence, 

The schematic here looks mostly good. I have a few changes to recommend. See my notes below:

• Decoupling capacitors included.
  • Please use 0.1uF capacitors for Vcc, Vio, and Vsup decoupling close to device pin.
• Termination resistors would be better placed on the connector-side of the CMC.
  • Ideal placement for the common mode choke is as close to the transceiver pins as possible. This ensures all of the current that flows through the network termination flows through the CMC and sees the benefit of this passive component.
• Split capacitor included and valued appropriately.
• Bus capacitors included and valued appropriately for a small-to-mid sized system - ensure placement close to connector and along signal path.
• No TVS diode included - no issue if internal protection is sufficient for application.
• Termination resistors included correctly and valued appropriately.
  
  • Consider including footprint for optional TVS diode. Please promote TI's ESD2CAN24 for CAN applications.
• All pull-up / series resistances are acceptable.
  • Capacitors on digital signal lines (TXD/RXD) can cause high outrush currents through the digital pin drivers, stressing the pins. To slow edges of digital signals, small series resistances are recommended. 10-ohm - 33-ohm are typical values. Resistor should be placed near signal driver (near transceiver for RXD, MCU for TXD).

Lawrence He said:

• How to placement termination resistors? Follow EVB termination resistors near transceiver IC or datasheets chapter 13 “Layout”  (near connector)?
• About SPI. Is only nINT/SDO need external pull-up 10k ohm (inner open drain)? Other pins can use internal pull-up resistors(~350 k ohm)? (Datasheet Figure 10-5. ;REVISED MARCH 2022)
• About INH pin, need external pull-down 100k ohm for inner PMOS open drain.

I recommend placing termination resistors on the connector-side of the CMC similar to the datasheet recommendation. Note that the EVM is not ideal for layout guidelines as its primary purpose is for accessibility for evaluation and testing. Application layouts may use different techniques to achieve best system results (but will not be as test friendly). 

Correct, only the nINT pin has an open-drain configuration which requires an external pull-up. All other SPI signal can be left with no external bias. 

The INH pin has an integrated 10M-ohm pull-down resistor. External pull-downs are still recommended to lower the transition time of the signal when the INH pin goes to a high-z state when disabled. 

Lawrence He said:

• I only can image, a mechanical if can provide voltage transition will trigger that device wake-up, right?
• The “WAKE”  detection “H”(“L”) to “L”(“H”) (VHmin = Vsup-2V, VLmax = Vsup-3.5V) divider from Vsup.
• How to design “WAKE” pins parallel capacitor? Datasheet is 22nF. But EVM is 0.01uF. Which is better

The WAKE circuit on the datasheet is primarily designed for mechanical switches that would have significant debounce requirements and inrush current limiting considerations. For more controlled signal sources, less filtering is needed. If no local wake signal is used, the WAKE pin may be tied to ground for the best power performance in low power mode. 
Note that the divider for Vsup is not needed for any device operation, so if no wake source is unused on the local board this pin should be tied to ground. 

Let me know if you have any more questions. 

Regards, 
Eric Schott