DP83867CS: 1000Base-T Compliance Test Difference A,B Peak Output Voltage FAIL

Hi User,

The 1000Base-T Compliance spec is tight but I believe we can resolve this. Is every other test passing except for this Peak A/B difference? If so then we're in pretty good shape, as the failure right now is marginal in my opinion. Just to confirm, are we using the script provided in SNLA239 ? 

If so, could you add an extra register write? After Reg 0x1F = 8000, write Reg 0x0 = 0140. Please let me know how this affects the test.

Regards,

Alvaro

Hi Alvaro,

Thank you for answering.
We will answer below.

>The 1000Base-T Compliance spec is tight but I believe we can resolve this.
>Is every other test passing except for this Peak A/B difference?
All tests have not been completed, but only No. 4 of the 1000BASE test has been conducted.
Please refer to the attached file below.
Additionally, the current FAIL locations are the following two locations,
and MASTER JITTER (w/ TX_TCLK) will be measured at a later date.
<1000BASE FAIL ITEM>
・Difference A,B Peak Output Voltage(w/o Disturbing Signal)
・Difference A,B Peak Output Voltage(w/ Disturbing Signal)

>If so then we're in pretty good shape, as the failure right now is marginal in my opinion.
>Just to confirm, are we using the script provided in SNLA239 ?
>If so, could you add an extra register write? After Reg 0x1F = 8000, write Reg 0x0 = 0140.
>Please let me know how this affects the test.
We conducted the test according to the snla239b instructions below.
So I believe the above steps have been taken.
However, when we re-checked the ETHER compliance test procedure manual, we found that snla239c had been updated in 2023.
Should I follow the steps of snla239c below?
Also, could you please tell me why the test procedure was changed?

【1000 Base Test Mode 1 steps for snla239b】

【1000 Base Test Mode 1 steps for snla239c】

Best Regards,

Hi User,

Thank you for pointing that out, I will discuss internally with my team as to why this was removed. Please continue following the Rev B script. Could you please share the full report, where I can see the waveforms as well?

Regards,

Alvaro

Hi Alvaro,

Thank you for answering.
We will answer below.

>Could you please share the full report, where I can see the waveforms as well?
I would like to share the results I obtained with the Rev B script earlier.
Please see the results below.
Also, is it okay to share the report with the results of 1000 Base-T, difference A, B peak output voltage?
Please contact us if there is anything missing.

1.No4 test results
(1)Difference A,B Peak Output Voltage(w/o Disturbing Signal)
　①PAIRA
　No4_ETH_1G_TESTMODE1_PAIRA_DIF_PEAKA&B_WITHOUT_DUSTURB__1.pdf
　②PAIRB

　No4_ETH_1G_TESTMODE1_PAIRB_DIF_PEAKA&B_WITHOUT_DUSTURB_NG_1.pdf

　③PAIRC

　No4_ETH_1G_TESTMODE1_PAIRC_DIF_PEAKA&B_WITHOUT_DUSTURB_1.pdf

　④PAIRD

　No4_ETH_1G_TESTMODE1_PAIRD_DIF_PEAKA&B_WITHOUT_DUSTURB_1.pdf

(2)Difference A,B Peak Output Voltage(w/ Disturbing Signal)
　①PAIRA

　No4_ETH_1G_TESTMODE1_WITH_DISTURB_PAIRA_1.pdf
　
　②PAIRB

　No4_ETH_1G_TESTMODE1_WITH_DISTURB_PAIRB_1_NG.pdf

　③PAIRC

　No4_ETH_1G_TESTMODE1_WITH_DISTURB_PAIRC_1.pdf

　④PAIRD

　No4_ETH_1G_TESTMODE1_WITH_DISTURB_PAIRD_1.pdf

Best Regards,

Hi User,

Thank you for sending al the reports. Glad to see only Channel B is affected. Using the same revB script, instead of 0x25=0480, can you try 0x25 = 0x420?

This will output the waveform only to Channel B. Could you also share the schematic?

Regards,

Alvaro

Hi Alvaro,

Thank you for answering.
We will answer below.

>Glad to see only Channel B is affected. Using the same revB script, instead of 0x25=0480, can you try 0x25 = 0x420?
We configured the above registers on board No4.
Then, I confirmed on the oscilloscope that the waveform was output only on channel B.
After that, I tested it, but the result was FAIL.
We will share the results below.

1.Test Result
(1)Difference A,B Peak Output Voltage(w/o Disturbing Signal)
　①Board_No4
　②Test results
　　Number of tests: POINTA[mV], POINTB[mV]
　　　　　 1st time: 　700.1 　　,　718.9　　 　：FAIL
　　　　　 2nd time: 　700.1 　　,　717.5　　　：FAIL
　　　　　 3rd time: 　700.3　　 , 　716.7　　　：FAIL
　③Report file
　　·First time

　　No4_ETH_1G_TESTMODE1_REG0x25_0x420_PAIRB_WITHOUT_DISTURB_NG_1.pdf

 　　·Second time

　　No4_ETH_1G_TESTMODE1_REG0x25_0x420_PAIRB_WITHOUT_DISTURB_NG_2.pdf

  　 ·Third time

　　No4_ETH_1G_TESTMODE1_REG0x25_0x420_PAIRB_WITHOUT_DISTURB_NG_3.pdf

>Could you also share the schematic?
A circuit diagram is attached below.

schematic_ETHER_240422.xlsx

We will also share the results of implementing "schematic checklist, layout checklist" etc. in the thread below.
Please see the thread below for details.
<e2e>
https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1343001/dp83867cs-10base-te-compliance-test-peak-difference-voltage-result-fails/5145034?tisearch=e2e-sitesearch&keymatch=%252520user%25253A431079#5145034

Best Regards,

Hi User,

Thank you for the reports and schematics. Please allow me until the end of week to review your schematic.

Regards,

Alvaro

Hi Alvaro,

Thank you for answering.

>Please allow me until the end of week to review your schematic
Thank you for confirming the above.

We are also conducting a bug analysis regarding this issue.
We performed the following analysis on CHANNELA of board No. 13, which had a problem.
Please also share the following content.

1.Test items
・1000 Base-T, difference A, B peak output voltage (w/o Disturbing Signal)

2. Exam content ①
(1) Normal compliance test
・A normal compliance test was conducted using TEST FUXTURE on CHANNELA with the following configuration.
　(Measurement system: Figure 1)

(2) Test results
・The difference between POINTA and POINTB was about 20mV at the PHY output end, resulting in a FAIL.

3. Exam content ②
(1) Compliance test at the PHY output end
Next we removed the external filter to see if there was a problem with PAIRA's MDI line.
Then, the PHY PAIRA output end was terminated with AC coupling and 100Ω, and the Difference A,B Peak Output Voltage was measured.
The above measured values do not include transformers, external filters, connectors, etc.

(Measurement system: Figure 2)

(2) Test results
・The difference between POINTA and POINTB was about 20mV at the PHY output end, resulting in a FAIL.

The differences between POINTA and B of test content ① and test content ② above were almost the same.
Therefore, I think that the cause is a deviation of about 20mV at the PHY output end.
Please tell me the reason for the deviation of about 20mV at the PHY output end.
Based on the above results, please let me know any improvement measures.

Best Regards,

Hi User,

I will review the schematic first before commenting on your most recent post. I will respond again before end of week.

Regards,

Alvaro

Hi User,

I reviewed the MDI portion of your schematic and I have a question about the multiple CMCs you have. You have one before the magnetic, one included in the magnetic, and another one after the magnetic (before the connector). Could we try removing the third magnetic in front of the connector?

Could you also try the following independently and together to see how it affects the result?

• increasing Reg A0 before the test? Read it's current value and increase it by 2. E.g. If default value is 705, increase to 707.
• setting Reg 0x25 = 0400. This outputs only to Channel A, instead of all channels. 

Regards,

Alvaro

Hi Alvaro,

Thank you for answering.
Please tell me about the following.

It would be troublesome to do it again, so please check the following points.

【Confirmation details 1】
>Could we try removing the third magnetic in front of the connector?
We would like to confirm the difference A, B peak output voltage (w/o Disturbing Signal) test with the configuration below.
Also, is the exam structure correct?

【Confirmation details 2】
The board where CHANNELA fails is No.13.
I'm thinking of performing the above confirmation on board No. 13, is that ok?

【Confirmation details 3】
I am thinking of trying the contents in the table below.
Are the following contents appropriate?

【Confirmation details 4】
Please share your schematic verification results.
Also, were there any problems with this issue?

【Confirmation details 5】
Could you please give me the answer to [Question 2]?
I think we have a similar problem.
Please let me know how it has been improved.

【Confirmation details 6】
According to the previous survey results the differences between POINTA and B of test content ① and test content ② above were almost the same.
Therefore, I think that the cause is a deviation of about 20mV at the PHY output end.
Please tell me the reason for the deviation of about 20mV at the PHY output end.

Also, since I will be away on vacation starting next week, I will respond after May 7th.

Best Regards,

Hi User,

Your exam structure is correct. Using board no. 13 is okay and the contents (different values of A0) is good. A0 and A1 will help tune the out voltage.

Connecting the 100 ohm between differential pair A confirms it is the PHY's output. I would like to confirm what scope settings you're using to run this test.

Enjoy your vacation!

Regards,

Alvaro

Hi Alvaro,

Thank you for answering.

We conducted tests with the above register settings on the No. 13 board.
However, even after adjusting the VOD, the result was FAIL.
We will share the results below.

1.TEST RESULT

2.Report file
(1)When setting A0[3:0]_0x07
No13_ETH_1G_TESTMODE1_REG0x25_0x400_REG0xA0_0x0707_PAIRA_WITHOUT_DISTURB_NG_1.pdf

(2)When setting A0[3:0]_0x09
No13_ETH_1G_TESTMODE1_REG0x25_0x400_REG0xA0_0x0709_PAIRA_WITHOUT_DISTURB_NG_1.pdf

(3)When setting A0[3:0]_0x0B
No13_ETH_1G_TESTMODE1_REG0x25_0x400_REG0xA0_0x070B_PAIRA_WITHOUT_DISTURB_NG_1.pdf

(4)When setting A0[3:0]_0x0D
No13_ETH_1G_TESTMODE1_REG0x25_0x400_REG0xA0_0x070D_PAIRA_WITHOUT_DISTURB_NG_1.pdf

(5)When setting A0[3:0]_0x0E
No13_ETH_1G_TESTMODE1_REG0x25_0x400_REG0xA0_0x070E_PAIRA_WITHOUT_DISTURB_NG_1.pdf

(6)When setting A0[3:0]_0x0F
No13_ETH_1G_TESTMODE1_REG0x25_0x400_REG0xA0_0x070F_PAIRA_WITHOUT_DISTURB_NG_1.pdf

From the above results, the differential voltage increases by adjusting VOD.(Except for the 0x0F setting)
However, there was no change in the difference between POINTA and B.
Similar to the previous verification results, we can see that there is a deviation of about 20mV at the PHY output end.
Therefore, I think that the cause is a deviation of about 20mV at the PHY output end.
Please tell me the cause of the deviation of about 20mV at the PHY output end and how to improve it.

Also, we don't understand why you haven't answered our questions.
Could you please answer the following questions?

--------------------------previous question----------------------
【Confirmation details 4】
Please share your schematic verification results.
Also, were there any problems with this issue?

【Confirmation details 5】
Could you please give me the answer to [Question 2]?
I think we have a similar problem.
Please let me know how it has been improved.

【Confirmation details 6】
According to the previous survey results the differences between POINTA and B of test content ① and test content ② above were almost the same.
Therefore, I think that the cause is a deviation of about 20mV at the PHY output end.
Please tell me the reason for the deviation of about 20mV at the PHY output end.
------------------------------------------------------------------

Best Regards,

Hi User,

Welcome back! I did not see this until the end of day, will reply tomorrow. Thank you for your patience.

Regards,

Alvaro

Hi User,

Please find our DP83867 PMA Report attached. Before I instructed to increase Reg 0xA0 values, could we perform the test again by decreasing the values instead? To simplify everything can we focus on running the tests on the Compliance test fixture to reduce the number of "moving parts". On a side note, I took the TMDS64EVM which has a DP83867 onboard and ran the compliance test on it. It also passed (using the script from SNLS239B).

Regards,

Alvaro

Hi Alvaro,

Thank you for answering.

>Before I instructed to increase Reg 0xA0 values, could we perform the test again by decreasing the values instead?
I tested with the following register settings on board 13.
However, although the difference between POINTA and B decreased, the result was FAIL.
Also, there was no change in MARGIN.

We will share the results below.

1.TEST RESULT

2.Report file
(1)When setting A0[3:0]_0x05
No13_ETH_1G_TESTMODE1_REG0x25_0x400_REG0xA0_0x0705_PAIRA_WITHOUT_DISTURB_NG_1.pdf

(2)When setting A0[3:0]_0x03
No13_ETH_1G_TESTMODE1_REG0x25_0x400_REG0xA0_0x0703_PAIRA_WITHOUT_DISTURB_NG_1.pdf

(3)When setting A0[3:0]_0x01
No13_ETH_1G_TESTMODE1_REG0x25_0x400_REG0xA0_0x0701_PAIRA_WITHOUT_DISTURB_NG_1.pdf

>Please find our DP83867 PMA Report attached.
>On a side note, I took the TMDS64EVM which has a DP83867 onboard and ran the compliance test on it.
>It also passed (using the script from SNLS239B).
We are currently confirming the above.

Best Regards,

Hi User,

Can we also try setting the output to single channel (instead of all channels) and decreasing the value of Reg 0xA3, this it to tune the filter setting.

Regards,

Alvaro

Hi Alvaro,

Thank you for answering.

I have some questions about the above instructions, so please let me know the following:

>Can we also try setting the output to single channel (instead of all channels)
Is my understanding correct that the above instructions are to set 0x400 to TESTMODE_CTRL_REG (ADRRESS=0x25)?

>and decreasing the value of Reg 0xA3, this it to tune the filter setting.
I checked the data sheet, but there was no mention of address 0xA3.
Please tell me the following points.
When I read REG 0xA3, I saw a value of 0x1010.
Please tell me how should I decrease the value.
Also, is the adjustment register for this filter the 16-bit data of  0xA3[15:0]?

Best Regards,

Hi User,

Alvaro will be OoO for the week and will be returning next week. Please expect delay. To help move the conversation forward:

It does appear that Reg 0x25 command is correct. You may validate this against your setup where the other channels should be silent.

Do you see on your side that if all channels are enabled (Reg 0x25 = 0x480), that this symmetry is worse?

There will be new information coming out in the latest revision of the datasheet, but for Channel A, Reg 0xA2[13] needs to be enabled, and if so, then adjust [12:8] down relative to its default value. For example, If Reg 0xA2 default is 0x1010, then to adjust lower by one click, the value should be 0x2E10.

Sincerely,

Gerome

Hi Gerome,

Thank you for answering.
We will answer below.

>Alvaro will be OoO for the week and will be returning next week. Please expect delay.
I understand the above matter.

>Do you see on your side that if all channels are enabled (Reg 0x25 = 0x480), that this symmetry is worse?
I tested again.
As a result, the difference between POINTA and POINTB of Difference A,B Peak Output Voltage did not change.
Also, from the results below, there was a difference of about 20mV.
Therefore, I think that even if all channels are set to enabled (REG0x25=0x480), the symmetry will not deteriorate.

>There will be new information coming out in the latest revision of the datasheet, but for Channel A,
>Reg 0xA2[13] needs to be enabled, and if so, then adjust [12:8] down relative to its default value.
>For example, If Reg 0xA2 default is 0x1010, then to adjust lower by one click, the value should be 0x2E10.
The results of testing after changing Reg 0xA2[13:8] are reported below.
However, the difference between A and B did not change the peak output voltage.
I suspect that the channel A register is wrong.

Due to the above result, I changed REG_0xA2[5:0] and conducted a test.
Since the Difference A,B Peak Output Voltage was changing, I think the register settings for channel A are valid.
Regarding the register of channel A, is REG_0xA2[5:0] correct?

　
Also, from the above results, by reducing the FILTER adjustment register (0xA2[5:0]),
We assume that the difference between POINTA and POINTB will be smaller, but the margin will remain the same.
What effect does this register REG_0xA2[15:0] have?
Is it a register to adjust the difference between POINTA and POINTB?

Best Regards,

Hello,

Thank you for the query. You are correct for Reg 0xA2 mapping, my apologies. This is for line driver filtering and has shown positive correlation for symmetry if you decrement it. You see that the margin has dropped by 0.1%. What happens if you implement this setting in conjunction with having all channel test setup (Reg 0x25)?

Sincerely,

Gerome

Hi Gerome,

Thank you for answering.
We will answer below.

>What happens if you implement this setting in conjunction with having all channel test setup (Reg 0x25)?
We configured and tested all channel setups (Reg 0x25=0x480) and FILTER adjustment registers (Reg 0xA2[5:0]).
As a result, the line driver's Difference Peak Output Voltage margin seemed to decrease by 0.1%.
Please see the results below.

Also, we have VOD adjustment (REG_A0[3:0]), FILTER adjustment register (REG_A2[5:0]), TESTMODE1 output channel setting (REG_0x25)
I changed it and checked the contents.
However, the margin between Difference between POINTA and POINTB has not been improved.
If there are any other settings that should be checked, please let us know.

We also share circuit diagrams, etc.
However, the confirmation results have not yet been shared.
For example, could you please let me know if there is any information on the crystal oscillator, power supply, RBIAS resistor, etc. on the circuit diagram that may have an effect on this problem?

Best Regards,

Hello,

Assuming this is the same design we had discussed in prior thread, I believe we had talked about the RBias resistor and Alvaro had also discussed concern with extra CMC. Have these points been resolved?

Sincerely,

Gerome

Hi Gerome,

Thank you for answering.
We will answer below.

>and Alvaro had also discussed concern with extra CMC.
yes. From Alvaro's answer, it seems that there is a concern about the external CMC filter.
Therefore, we remove the external CMC filter and perform the verification below.

1.Test content①
(1)Measurement point
・Measured at PHY output end

(2)Test configuration
・Remove external filter and measure at PHY output end

(3)Test results

◆From the above test results, it can be seen that there is a deviation of about 20mV at the PHY output end.

2.Test content②
(1)Measurement point
・Measured at the output end of Magnetics

(2)Test configuration
・Delete external Filter and change to 0Ω. and Measured at the output end of Magnetics

(3)Test results

◆From the above test results, it can be seen that there is a deviation of about 20mV at the output end of Magnetics.
Currently, we have received instructions to conduct verification tests with the above configuration.
Also, VOD adjustment (REG_A0[3:0]), FILTER adjustment register (REG_A2[5:0]), TESTMODE1 output channel setting (REG_0x25)
I changed it and tested it.
However, the difference between POINTA and POINTB was not improved.
Therefore, we believe that external CMC filters are not affected.
However, regarding the external filter, which was a concern, I have not been able to confirm it because Mr. Alvaro is on holiday this week.

3.Test content③
(1)Measurement point
・Measured at the end of the Test Fixture

(2)Test configuration
We carry out regular compliance tests.
In addition, we are conducting tests on CHANNELA using TEST FIXTURE with the following configuration.

(3)Test results

◆From the above test results, it can be seen that there is a deviation of about 20mV even at the TEST FIXTURE end.

From the above results, the differences between POINTA and B for test content ①, test content ②, and test content ③ were almost the same.
The difference between POINTA and B at the PHY output end was the same as the difference at the TEST FIXTURE end.
Therefore, I believe that the problem is that there is a difference between POINTA and B at the output end of the PHY.
Therefore, the difference between POINTA and POINTB at the output end of the PHY is about 20mV, so unless this difference is reduced,
I don't think this problem will go away.

>Assuming this is the same design we had discussed in prior thread,
yes. A similar thread below.
We are also sharing this thread (Schematic Checklist and LAYOUT Checklist).

<e2e>
https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1343001/dp83867cs-10base-te-compliance-test-peak-difference-voltage-result-fails/5145034?tisearch=e2e-sitesearch&keymatch=%252520user%25253A431079#5145034

>I believe we had talked about the RBias resistor
No.
We share schematics, checklists, test results, and more.
However, even if I ask again about the check results, I have not received an answer.
Therefore, the test was not conducted by changing the RBIAS resistance (10KΩ + 1KΩ → 11KΩ + 0Ω).
Is it better to perform the above test?
Also, the difference between POINTA and POINTB at the PHY output end is off by about 20mV, so I would like to check whether there is a problem with the PHY circuit configuration.
Therefore, we would like to know the results of checking the circuit diagram below.

Best Regards,

Hello,

Our best guidance would be to use a 11k resistor as the 10k+1k could have individual variances which compound, thus providing an unideal RBIAS value for the PHY. I would recommend seeing if a 11k with solder short would have any change in effect.

Sincerely,

Gerome

Hi Gerome,

Thank you for answering.
We will answer below.

>I would recommend seeing if a 11k with solder short would have any change in effect.
In board 13, the RBIAS resistance was changed from 10KΩ+1KΩ to 11KΩ±0.5%.
Then, I checked that the RBIAS voltage was 1.006V and ran the test.
However, the difference between POINTA and POINTB remained unchanged at 20mV, and the result was FAIL.

1. How to change RBIAS resistance
・10KΩ and 1KΩ have been deleted and 11KΩ ±0.5% products are installed as shown below.

2. Test confirmation results
・Please refer to the results below.

From the above results, it seems that RBIAS resistance is not affected.
Also, please let me know if there are any other points I should check.

Best Regards,

Hello,

Thank you for our reply. We will respond next week with further experiments. Can you please provide how many boards are you seeing this issue on?

Sincerely,

Gerome

Hi Gerome,

Thank you for answering.
We will answer below.

>Can you please provide how many boards are you seeing this issue on?
4 out of 6 boards failed in the Difference A,B Peak Output Voltage (w/o Disturbing Signal) test.
Also, the ports that were FAIL had different locations in CHANNELA, B, and D.
Please refer to the results below for details.

Best Regards,

Hi User,

I am back today, please allow me another day to review what Gerome suggested and get reply to your most recent post.

Regards,

Alvaro

Hi User,

I want to somewhat reset this thread and start from basics again. You have 4 boards out of 6 failing Peak A & B Symmetry. I still have your schematic file that I can double check again but did you ever send the layout? I found the filled out layout checklist but is there a way to send the file itself for me to review?

Regards,

Alvaro

Hi Alvaro,

Thank you for answering.

We will share the PCBLAYOUT diagram below.
Please refer to the materials below.

PCB_LAYOUT_240522.xlsx

Best Regards,

Thank you User,

Please find my comments attached regarding the schematic. Please allow until end of week to review layout. 

DP83867_Schematic_Design_Review_Olympus.xlsx

Regards,

Alvaro

Hi Alvaro,

Thank you for answering.
We will answer below.

>Please find my comments attached regarding the schematic
We have provided answers to the questions in the "TI FEEDBACK column" in the attached schematic checklist below in the "J column (customer answer)".
Please check the attached file below.

DP83867_Schematic_Design_Review_Olympus_240523.xlsx

【Question3】
Please tell me about the check results on the circuit diagram.
Did you find anything that might affect this issue?

Best Regards,

Hi User,

Thank you for the feedback in the schematic. Like last time there was nothing here to hint at the issue. I have not completed my review of the layout, will reply again tomorrow.

Regards,

Alvaro

Hi User,

Thank you for sharing the layout files. I see that the board has 10 layers and Channel C & A go from Layer 1 to Layer 10, then back up to Layer 1. This may have an marginal effect. To your credit, Layer 2 & 9 are solid ground planes which is excellent practice. 

Could we enable Mirror mode and see if the problem changes to a different channel (Reg 0x31[0] = '1')?

Regards,

Alvaro

Hi Alvaro,

Thank you for answering.
We will answer below.

>Could we enable Mirror mode and see if the problem changes to a different channel (Reg 0x31[0] = '1')?
Below we share the results of a test we conducted with MIRROR_MODE (0x31) set to "1" (ENABLE).
We also believe that when Mirror mode is enabled, CHANNEL "ABCD" becomes the output of "DCBA", and the positive and negative are inverted.
As the above showed that the waveforms of POINT A and B of the test signal in TESTMODE1 were also inverted, we inverted the probe head (P/N) of the differential probe and connected it to the texture before conducting a test.
Please let us know if there are any problems with the test procedure.

The results showed that the difference between POINT A and B was smaller when MIRROR was ON than when MIRROR was OFF.
However, I suspect the channel in question hasn't been migrated to another channel.
Please see the results below.

We would like to know why the difference between POINT A and B becomes smaller when MIRROR MODE is set to ENABLE.
If you find out why the difference between POINT A and B becomes smaller, could you please let us know?

Best Regards,

Hi User,

There have been several compliance "miracles" that have left my team and I speechless. We are in contact with our design team to get an explanation, but the answer will most likely be due to some internal function of the PHY that cannot be publicly shared.

Just to confirm, the results above were achieved by using the script below, along with mirror mode enable, and nothing else correct? If so could we revisit the registers Gerome mentioned to tune the failing board? (Reg 0xA0, A1, etc.)

Regards,

Alvaro

Hi Alvaro,

Thank you for answering.
We will answer below.

>Just to confirm, the results above were achieved by using the script below,
>along with mirror mode enable, and nothing else correct?
Yes, I did it following the steps below.

◇1000 Base Test Mode 1:
Reg 0x001F = 0x8000 //reset PHY
Reg 0x0031 = 0x10B1 //Mirror Mode Enable
Reg 0x0000 = 0x0140 //1000 Base-T Mode
Reg 0x0010 = 0x5008 //forced MDI Mode
Reg 0x0009 = 0x3B00 //Test Mode 1
Reg 0x0025 = 0x0480 //output test mode to all channels
Reg 0x01D5 = 0xF508

>If so could we revisit the registers Gerome mentioned to tune the failing board? (Reg 0xA0, A1, etc.)
We will check the above and report back at a later date.

Best Regards,

Thank you User,

Looking forward to seeing the results.

Regards,

Alvaro

Hi Alvaro,

Thank you for answering.
We will answer below.

>If so could we revisit the registers Gerome mentioned to tune the failing board? (Reg 0xA0, A1, etc.)
We have confirmed the above and are reporting it below.
We changed and checked the settings of the FILTER adjustment register (0xA2), VOD adjustment register (0xA1, 0xA0), etc., but the results (MARGIN rate, etc.) did not change.
In addition, the DP83867CS was tested in a single output state because the mirror mode ENABLE setting was enabled.
TESTMODE_CTRL_REG (0x25=0x460) was set to CHANNELD, and output was from CHANNELA.
For details, please refer to the results below.

Best Regards,

Hi User,

In Row 9 & 10 we achieved a passing result, with Reg 0xA2 = 2E & 2C. Is this a viable solution for you?

Regards,

Alvaro

Hi Alvaro,

Thank you for answering.
We will answer below.

>In Row 9 & 10 we achieved a passing result, with Reg 0xA2 = 2E & 2C. Is this a viable solution for you?
No, the above is not a viable solution.
Our answer consists of setting MIRROR MODE to OFF. We believe that you need to test with MIRROR MODE OFF and pass it.
Also, [1000 Base-T, difference A, B peak output voltage (w/o Disturbing Signal)] is a simple test,
so [1000 Base-T, difference A, B peak output voltage (w/ Disturbing Signal)] needs to pass.
However, we performed the above test and it was FAIL.
Please refer to the results below.

Please answer the questions below.

[Question 4]
Our circuit is configured with MIRROR MODE OFF.
Therefore, we believe it is necessary to turn the MIRROR MODE OFF and perform the test in order to pass.
Also, we believe that the above procedure is a test procedure that is not described in the data sheet.
Is it correct to perform the test with MIRROR MODE ON?

[Question 5]
From the measurement results so far, there were multiple locations where POINT A and POINT B in CHANNEL A to D failed or had no margin due to the DP83867 parts.
I also tried measuring with the DP83867ERGZ-S-EVM.
With the DP83867ERGZ-S-EVM, there was also variation between POINT A and POINT B in CHANNEL A to D, and some locations had no margin.
There was also variation when comparing the CHANNELD results for BORD_No "#7416100018" and "#7416100205".
The measurement results for the DP83867ERGZ-S-EVM also suggest that there is variation in the difference between POINT A and B for each CHANNEL.
Can we assume that the difference between POINTA and POINTB is caused by the PHY components?
Please refer to the results below.

[Question 6]
We have had you check the circuit diagram and AW diagram.
However, we have still not been able to identify the cause of this problem.
Is there any other way to improve it?

Best Regards,

Hi User,

Apologies for my delay in response.

Leaving mirror mode on is okay for testing. 

The variation between Point A/B among the different channels is to be expected. This is caused by PHY components.

Have you run the disturber signal on our EVM?

Based off the EVM results vs your Board, it still leads me to believe that layout has a big impact.

Regards,

Alvaro

Hi Alvaro,

Thank you for answering.
We will answer below.

>The variation between Point A/B among the different channels is to be expected.
>This is caused by PHY components.
>Based off the EVM results vs your Board, it still leads me to believe that layout has a big impact.
Given the above answers, we performed ABA testing to isolate the cause to the PHY device.
We moved the failed devices from the prototype board to a TI evaluation board (DP83867ERGZ-S-EVM) and confirmed the results were failed on the DP83867ERGZ-S-EVM.
We also confirmed that when we moved some parts that passed on the DP83867ERGZ-S-EVM to the prototype board, the channels that failed on the prototype board were improved and passed. The test results showed that the symptoms differed depending on the device.
Please see the results below.

*By replacing the PHY parts, CHANNELC changed from PASS to FAIL.
From the above, we can see that the malfunction phenomenon is transferred by replacing the faulty PHY part in the DP83867ERGZ-S-EVM.

*By replacing the PHY parts, CHANNELC changed from FAIL to PASS.

Based on the above results, we believe that there is a high possibility that the cause is variation in the DP83867CS product.
Therefore, we believe that the failure is not due to the board layout, but due to variation in the PHY components.
Therefore, we would like to determine as soon as possible whether or not the DP83867CS product can be used.

Please tell me the following information:

[Question 7]
You have checked the circuit diagram and artwork, but have not found a solution to the problem.
Do you have any suggestions for resolving this issue?

[Question 8]
Our board uses a CS product of DP83867.
We checked TI's evaluation board (EVM) and compliance results (DP83867 PMA Report ), and found that an E product was used.
Will replacing it with an E product or similar improve this issue?

[Question 9]
We previously received the following response from you via e2e.

What are the results of this confirmation?
Is the cause of the current problem due to the above content?

Best Regards,

Hi User,

From your tests it does seem like the E version of the part performs better. I have discussed with the product team and they have told me that aside from the temperature testing, all other tests are the same. I will need to discuss with my team regarding this matter, please allow me another day to reply.

Regards,

Alvaro

Hi User,

There is definitely variation between parts, but switching to the E version will not guarantee better compliance performance. I reconfirmed with my team, aside from temperature testing, all versions (C/I/E) undergo the same electrical testing.

The compliance test waveform isn't a functional waveform, therefore enabling/disabling features to run the test is acceptable; i.e. disabling auto-negotiation, outputting to a single channel, and enabling mirror mode. If you want all your boards to pass compliance, then the registers (A0, A1, etc) will need to be tuned for each specific board, since these are trim values (same way you got board 13 to pass in Figure 1).

Figure 1 - Board 13 Filter and VoD register test

That being said, the failure is still marginal and will not cause functional issues. Has there been any functional issues?

Regards,

Alvaro

Hi Alvaro,

Thank you for answering.
We will answer below.

Alvaro (Al-vuh-roe) Reyes said:

There is definitely variation between parts, but switching to the E version will not guarantee better compliance performance. I reconfirmed with my team, aside from temperature testing, all versions (C/I/E) undergo the same electrical testing.

Thank you for your reply. We understand the above.

Alvaro (Al-vuh-roe) Reyes said:

That being said, the failure is still marginal and will not cause functional issues. Has there been any functional issues?

This is currently in the prototype stage, so it is unclear whether this defect will cause any functionality issues.

Alvaro (Al-vuh-roe) Reyes said:

 If you want all your boards to pass compliance, then the registers (A0, A1, etc) will need to be tuned for each specific board, since these are trim values (same way you got board 13 to pass in Figure 1).

We realized that if the compliance test failed, we would need to adjust VOD, FILTER, and MIRROR individually.
We also learned that there is variation in output depending on the PHY components on the market, and that an additional evaluation process is required each time the product is shipped.
However, I believe that it would be difficult to individually adjust the VOD, FILTER, MIRROR, etc. in the case of a FAIL part.
Is it possible to get just the parts that pass all the requirements?

Based on the above, we are also considering switching to another PHY product, DP83869HM.
Please let us know the following points about the DP83869HM product.

[Question 10]
Regarding the DP83869HM, are there any compliance test results available when an external transformer is used?

[Question 11]
Regarding the DP83869HM, we are also considering an AC-coupled configuration without an external transformer.
Are there any compliance test results without an external transformer?

[Question 12]
The data sheets for the DP83869HM and DP83867CS only listed the MIN and MAX values ​​of Vpeak Defferential.
However, there was no mention of the difference in output between POINTA and POINTB in the Difference A,B Peak Output Voltage test.
The data sheets contain similar information, but will the same problem that occurred this time occur again?
◇DP83867CS data sheet (excerpt)

◇DP83869HM data sheet (excerpt)

Best Regards,

Hi User,

Thank you for your reply. The DP83869HM is an excellent part. Please allow me another day to gather the information for Questions 10, 11, and 12.

Regards,

Alvaro

Hi User,

10. I ran compliance on our DP83869EVM, please find the result attached. A more detailed report from UNH will require an NDA to be shared.

DP83869 1000BaseT PMA Compliance- Test Mode 1.pdf

11. The DP83869 supports capacitive coupling, but we do not have Compliance results for this configuration.

12. The Peak Point A & B will not be in the data sheet, as this is part of a compliance test and not a functional waveform.

Regards,

Alvaro

Hi Alvaro,

Thank you for answering.
We will answer below.

Please tell me about the following:

[Question 13]
Please tell me whether the DP83869EVM has passed all 10BASE-Te, 100BASE, and 1000BASE-T ETHER compliance tests.

[Question 14]

Alvaro (Al-vuh-roe) Reyes said:

10. I ran compliance on our DP83869EVM, please find the result attached. A more detailed report from UNH will require an NDA to be shared.

DP83869 1000BaseT PMA Compliance- Test Mode 1.pdf

I checked the results of running compliance using the attached DP83869EVM.
However, there were only compliance test results for 1000BASE-T TESTMODE1 without_Disturber.
Do you have any results for 1000BASE-T TESTMODE1 with_Disturber run on the DP83869EVM?
Also, do you have any compliance results for 10BASE-Te, 100BASE, and 1000BASE-T run on the DP83869EVM?

[Question 15]

Alvaro (Al-vuh-roe) Reyes said:

12. The Peak Point A & B will not be in the data sheet, as this is part of a compliance test and not a functional waveform.

I understand that the above is not mentioned in the datasheet.
Could you please let me know if the DP83869HM will have the same problem as the DP83867CS due to variations in PHY parts?

[Question 16]

user6236094 said:

However, I believe that it would be difficult to individually adjust the VOD, FILTER, MIRROR, etc. in the case of a FAIL part.
Is it possible to get just the parts that pass all the requirements?

Please also let me know the answer above.

Best Regards,