SN65DSI85: SN65DSI85 ref clk

Dany Vak

Part Number: SN65DSI85

Hi Team

I have a problem with the SN65DSI85-Q1, I can't lock on the mipi clk. The value of the mipi clk is around 150MHz, I can measure the frequency with the scope, but I can't get pll locked. The bit 0 in the E5 register is always 1, after I write FF into the register. The equalization (register 0x11) doesn't help. I used a dsi tuner and read a datasheet to create an initialization sequence.

The mipi clk can be used even to read a test pattern, but I can't use it to read an actual input data.

I can get a data in the FPGA when I use a REFCLK X 2 (I use an evaluation board, 27MHz X 2 = 54MHz), but in this case lvds clk slightly higher than actual pixel clk, which is around 150MHz/3 = 50MHz. I wanted to understand what happening in this case: do I get some padding (like blank pixels) or something else? Can I work in this mode? What will be effect on the picture?

Regards

Dany

over 1 year ago

0 Vishesh Pithadiya over 1 year ago

TI__Mastermind 43736 points

Hey Dany,

Just want to confirm the by test pattern do you mean the internal color bar pattern? If you are able to get the color bar to display, but cannot get data across this is most likely dues to a timing problem. Can you send me the panel spec, and what register configuration of the DSI85?

0 Dany Vak over 1 year ago in reply to Vishesh Pithadiya

Prodigy 40 points

Hi Vishesh

Yes, the test pattern is the internal color bar pattern.

I will attach a I2C aardvark file, thanks.

Fullscreen aardvark.xml Download

<aardvark>
<configure i2c="1" spi="1" gpio="0" tpower="1" pullups="1" />
<i2c_bitrate khz="100" />
=====SOFTRESET=======
<i2c_write addr="0x2D" count="1" radix="16">09 01</i2c_write>
<sleep ms="10" />
======ADDR 0D======= ======PLL_EN(bit 0) - Enable LAST after addr 0A and 0B configured======
<i2c_write addr="0x2D" count="1" radix="16">0D 00</i2c_write>
<sleep ms="10" />
======ADDR 0A======= ======HS_CLK_SRC bit0=== ======LVDS_CLK_Range bit 3:1======
<i2c_write addr="0x2D" count="1" radix="16">0A 03</i2c_write>
<sleep ms="10" />
======ADDR 0B======= ======DSI_CLK_DIVIDER bit7:3===== ======RefCLK multiplier(bit1:0)======
======00 - LVDSclk=source clk, 01 - x2, 10 -x3, 11 - x4======
<i2c_write addr="0x2D" count="1" radix="16">0B 10</i2c_write>
<sleep ms="10" />
======ADDR 10======= ======DSI Ch Confg Left_Right Pixels(bit7 - 0 for A ODD, B EVEN, 1 for the
other config)====== ======DSI Ch Mode(bit6:5) 00 - Dual, 01 - single, 10 - two single =======
======CHA_DSI_Lanes(bit4:3), CHB_DSI_Lanes(bit2:1), 00 - 4, 01 - 3, 10 - 2, 11 - 1
======SOT_ERR_TOL_DIS(bit0)=======
<i2c_write addr="0x2D" count="1" radix="16">10 26</i2c_write>
<sleep ms="10" />
<i2c_write addr="0x2D" count="1" radix="16">11 FF</i2c_write>
<sleep ms="10" />
======ADDR 12=======
<i2c_write addr="0x2D" count="1" radix="16">12 1D</i2c_write>
<sleep ms="10" />
======ADDR 18======= ======bit7: DE_Pol, bit6:HS_Pol, bit5:VS_Pol, bit4: LVDS Link Cfg, bit3:CHA
24bpp, bit2: CHB 24bpp, bit1: CHA 24bpp fmt1, bit0: CHB 24bpp fmt1======
<i2c_write addr="0x2D" count="1" radix="16">18 78</i2c_write>
<sleep ms="10" />
======ADDR 19=======
<i2c_write addr="0x2D" count="1" radix="16">19 00</i2c_write>
<sleep ms="10" />
======ADDR 1A=======
<i2c_write addr="0x2D" count="1" radix="16">1A 03</i2c_write>
<sleep ms="10" />
======ADDR 20======= ======CHA_LINE_LENGTH_LOW========
<i2c_write addr="0x2D" count="1" radix="16">20 C0</i2c_write>
<sleep ms="10" />
======ADDR 21======= ======CHA_LINE_LENGTH_HIGH========
<i2c_write addr="0x2D" count="1" radix="16">21 03</i2c_write>
<sleep ms="10" />
======ADDR 22======= ======CHB_LINE_LENGTH_LOW========
<i2c_write addr="0x2D" count="1" radix="16">22 00</i2c_write>
<sleep ms="10" />
======ADDR 23======= ======CHB_LINE_LENGTH_HIGH========
<i2c_write addr="0x2D" count="1" radix="16">23 00</i2c_write>
<sleep ms="10" />
======ADDR 24======= ======CHA_VERTICAL_DISPLAY_SIZE_LOW========
<i2c_write addr="0x2D" count="1" radix="16">24 D0</i2c_write>
<sleep ms="10" />
======ADDR 25======= ======CHA_VERTICAL_DISPLAY_SIZE_HIGH========
<i2c_write addr="0x2D" count="1" radix="16">25 02</i2c_write>
<sleep ms="10" />
======ADDR 26======= ======CHB_VERTICAL_DISPLAY_SIZE_LOW========
<i2c_write addr="0x2D" count="1" radix="16">26 00</i2c_write>
<sleep ms="10" />
======ADDR 27======= ======CHB_VERTICAL_DISPLAY_SIZE_HIGH========
<i2c_write addr="0x2D" count="1" radix="16">27 00</i2c_write>
<sleep ms="10" />
======ADDR 28======= ======CHA_SYNC_DELAY_LOW========
<i2c_write addr="0x2D" count="1" radix="16">28 20</i2c_write>
<sleep ms="10" />
======ADDR 29======= ======CHA_SYNC_DELAY_HIGH========
<i2c_write addr="0x2D" count="1" radix="16">29 00</i2c_write>
<sleep ms="10" />
======ADDR 2A======= ======CHB_SYNC_DELAY_LOW========
<i2c_write addr="0x2D" count="1" radix="16">2A 00</i2c_write>
<sleep ms="10" />
======ADDR 2B======= ======CHB_SYNC_DELAY_HIGH========
<i2c_write addr="0x2D" count="1" radix="16">2B 00</i2c_write>
<sleep ms="10" />
======ADDR 2C======= ======CHA_HSYNC_PULSE_WIDTH_LOW========
<i2c_write addr="0x2D" count="1" radix="16">2C 32</i2c_write>
<sleep ms="10" />
======ADDR 2D======= ======CHA_HSYNC_PULSE_WIDTH_HIGH========
<i2c_write addr="0x2D" count="1" radix="16">2D 00</i2c_write>
<sleep ms="10" />
======ADDR 2E======= ======CHB_HSYNC_PULSE_WIDTH_LOW========
<i2c_write addr="0x2D" count="1" radix="16">2E 00</i2c_write>
<sleep ms="10" />
======ADDR 2F======= ======CHB_HSYNC_PULSE_WIDTH_HIGH========
<i2c_write addr="0x2D" count="1" radix="16">2F 00</i2c_write>
<sleep ms="10" />
======ADDR 30======= ======CHA_VSYNC_PULSE_WIDTH_LOW========
<i2c_write addr="0x2D" count="1" radix="16">30 05</i2c_write>
<sleep ms="10" />
======ADDR 31======= ======CHA_VSYNC_PULSE_WIDTH_HIGH========
<i2c_write addr="0x2D" count="1" radix="16">31 00</i2c_write>
<sleep ms="10" />
======ADDR 32======= ======CHB_VSYNC_PULSE_WIDTH_LOW========
<i2c_write addr="0x2D" count="1" radix="16">32 00</i2c_write>
<sleep ms="10" />
======ADDR 33======= ======CHB_VSYNC_PULSE_WIDTH_HIGH========
<i2c_write addr="0x2D" count="1" radix="16">33 00</i2c_write>
<sleep ms="10" />
======ADDR 34======= ======CHA_HOR_BACK_PORCH========
<i2c_write addr="0x2D" count="1" radix="16">34 2C</i2c_write>
<sleep ms="10" />
======ADDR 35======= ======CHB_HOR_BACK_PORCH========
<i2c_write addr="0x2D" count="1" radix="16">35 00</i2c_write>
<sleep ms="10" />
======ADDR 36======= ======CHA_VER_BACK_PORCH========
<i2c_write addr="0x2D" count="1" radix="16">36 00</i2c_write>
<sleep ms="10" />
======ADDR 37======= ======CHB_VER_BACK_PORCH========
<i2c_write addr="0x2D" count="1" radix="16">37 00</i2c_write>
<sleep ms="10" />
======ADDR 38======= ======CHA_HOR_FRONT_PORCH========
<i2c_write addr="0x2D" count="1" radix="16">38 00</i2c_write>
<sleep ms="10" />
======ADDR 39======= ======CHB_HOR_FRONT_PORCH========
<i2c_write addr="0x2D" count="1" radix="16">39 00</i2c_write>
<sleep ms="10" />
======ADDR 3A======= ======CHA_VER_FRONT_PORCH========
<i2c_write addr="0x2D" count="1" radix="16">3A 00</i2c_write>
<sleep ms="10" />
======ADDR 3B======= ======CHB_VER_FRONT_PORCH========
<i2c_write addr="0x2D" count="1" radix="16">3B 00</i2c_write>
<sleep ms="10" />
======ADDR 3C======= ======CHA/CHB TEST PATTERN(bit4 CHA, bit0 CHB)========
<i2c_write addr="0x2D" count="1" radix="16">3C 00</i2c_write>
<sleep ms="10" />
======ADDR E0======= =====
<i2c_write addr="0x2D" count="1" radix="16">E0 01</i2c_write>
<sleep ms="10" />
======ADDR E1======= =====
<i2c_write addr="0x2D" count="1" radix="16">E1 FF</i2c_write>
<sleep ms="10" />
======ADDR E2======= =====
<i2c_write addr="0x2D" count="1" radix="16">E2 FF</i2c_write>
<sleep ms="10" />
======ADDR E5======= =====
<i2c_write addr="0x2D" count="1" radix="16">E5 FF</i2c_write>
<sleep ms="10" />
=======ADDR 0D======= ======PLL_EN(bit 0) - Enable LAST after addr 0A and 0B configured======
<i2c_write addr="0x2D" count="1" radix="16">0D 01</i2c_write>
<sleep ms="10" />
=====SOFTRESET=======
<i2c_write addr="0x2D" count="1" radix="16">09 00</i2c_write>
<sleep ms="10" />
======write======
<i2c_write addr="0x2D" count="196" radix="16">00</i2c_write>
<sleep ms="10" />
======Read======
<i2c_read addr="0x2D" count="256" radix="16">00</i2c_read>
<sleep ms="10" />
</aardvark>

This file is with the lvds clk derived from the mipi source.

I can't get a data in the FPGA, and a bit 0 in the E5 register is always 1

Once I change a 0x0A to 2, and 0x0B to the 0x10, I use a REFCLK, the data starts to arrive

Regards

Dany

0 Vishesh Pithadiya over 1 year ago in reply to Dany Vak

TI__Mastermind 43736 points

Hey Dany,

Are you able to share the panel spec. I want to verify the timing. It's odd that ref clock works and DSI clock doesn't. It seems there is a mismatch between the LVDS clock and the DSI clock timings

0 Dany Vak over 1 year ago in reply to Vishesh Pithadiya

Prodigy 40 points

Hi Vishesh

It's not exactly a panel, it's a our product, just a 720p stream.

0 Vishesh Pithadiya over 1 year ago in reply to Dany Vak

TI__Mastermind 43736 points

Is there a timing spec for your products? what is the criteria to pass a signal through. The DSI85 needs to have timing parameters entered for the DSI input and LVDS output using the DSI tuner tool. Im looking to verify these timings which may be the cause of the PLL drop.

0 Dany Vak over 1 year ago in reply to Vishesh Pithadiya

Prodigy 40 points

Hi Vishesh

Thanks for your reply

I've calculated a parameters using a DSI tuner and by myself. In both case DSI CLK was supposed to be around 150MHz, and LVDS/pixel clk around 50 MHz. We have something like 1024 pixels in row, 720 rows, 60 Hz refresh rate. mipi 4 lanes, and one lvds input (only the A input), 24 bit RGB.

+1 Vishesh Pithadiya over 1 year ago in reply to Dany Vak

TI__Mastermind 43736 points

Hey Dany,

Try using these timings CSRs I've generated. I added a padding of .33 around the active pixels as this is typical of a panel. This device is design to work with a panel, so that may have to do with the issue. Try using this CSR file as your setup and see if it works.

Fullscreen CSR_DANY.txt Download

//=====================================================================
// Filename   : CSR_DANY.txt
//
//   (C) Copyright 2013 by Texas Instruments Incorporated.
//   All rights reserved.
//
//=====================================================================
0x09              0x00
0x0A              0x03
0x0B              0x10
0x0D              0x00
0x10              0x26
0x11              0x00
0x12              0x1e
0x13              0x00
0x18              0x78
0x19              0x00
0x1A              0x03
0x1B              0x00
0x20              0x00
0x21              0x04
0x22              0x00
0x23              0x00
0x24              0x00
0x25              0x00
0x26              0x00
0x27              0x00
0x28              0x21
0x29              0x00
0x2A              0x00
0x2B              0x00
0x2C              0x70
0x2D              0x00
0x2E              0x00
0x2F              0x00
0x30              0x4f
0x31              0x00
0x32              0x00
0x33              0x00
0x34              0x70
0x35              0x00
0x36              0x00
0x37              0x00
0x38              0x00
0x39              0x00
0x3A              0x00
0x3B              0x00
0x3C              0x00
0x3D              0x00
0x3E              0x00


The PLL_EN bit and SOFT_RESET bit are not set as they need to be set per the recommended sequence defined in the datasheet

0 Dany Vak over 1 year ago in reply to Vishesh Pithadiya

Prodigy 40 points

Hi Vishesh

I still can't get pll locked, maybe because of the layout issue, but I started to get data in the FPGA.

Can you please explain in two words what is the register value which add this padding? I wasn't able to understand this from the datasheet.

Regards

Dany

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SN65DSI85: SN65DSI85 ref clk