• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 34 subscribers
  • Views 536 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

SN65DP159: DP159RGZEVM J2 Pin13 and Pin14

SN65DP159: SN65DP159RSBR SN65DP159RSBR I2C SRC Routing (Pins 38/39)

lu tan
Prodigy 160 points

Part Number: SN65DP159

Hi Forum,

I am making this thread as a verification that I have routing pins 38 and 39 correctly on the SN65DP159RSBR IC. These pins are the SCL and SDA lines for interfacing with DP source. While updating the CCA that uses this IC, I needed to reroute the trace connected to these two signals. In the previous layout, these lines were routed as differential pairs with controlled impedance. Due to limited spacing after updating the CCA, I cannot route these as controlled impedance anymore but just as regular SE traces.

I did not find anything about needing to route these pins as controlled impedance in the SN65DP159RSBR datasheet. However, looking through the HDMI spec, I found that this I2C signal along with the sink I2C signal is to run DDC bus functions such as reading EDID info from the HDMI sink. The DDC bus shall be run at 100k or 400k, which is Standard mode and Fast mode I2C. Such speeds do not need controlled impedance, hence I rerouted the traces connected to pins 38/39 of SN65DP159RSBR as regular traces.

I would like to receive verification that this is the correct design choice or whether I made the wrong choice and need to change these signals to differential pairs. Please advice.

Thank you,

Lu Tan 

  • 0
    TI__Guru 60236 points

    Hey Lu,

    Just want to confirm a few things. Would this be a good representation of you r system?

    Under the assumption your system is like the block diagram above, you are going from a DP++ source to a HDMI receptacle. If this is the case you will only need to worry about DDC as you will never have a DP sink connected to this system. This means routing pins 38/39 to the DPP++ source on the correct lanes should be fine. This means SCL is connected to  AUXp and SDA is connected to AUXn

  • 0 in reply to Vishesh Pithadiya
    Prodigy 160 points

    Hi Vishesh,

    The block diagram is correct. My question was more specifically whether the routing for these signals needed to have controlled impedance. My argument was that DDC was based on I2C protocol running at max 400kHz, and so does NOT need controlled impedance. Is my understanding correct?