DP83867CR: DP83867CR - difference in RGMII Transmit and receive clock skew details

Hi Sagar,

The strap pins for RGMII clock delays are GPIO_0/1 (RX) and LED_1/2 (TX) - can you clarify if these are the straps you are referring to without PU/PD?

It's possible there is another device or component on these pins that is affecting the sampled voltage on PHY startup.

Schematic can be shared at e-mayhew@ti.com so I may review the straps.

Thank you,

Evan

Hi Evan ,

Yes i checked GPIO 0/1 and LED 1/2 are having PU as per 101 configuration. Can you please let us know where i need to enter 3.5ns from firmware perspective so that my HW and SW are in sync?

Thanks

Sagar

Hi Sagar,

If you are running Linux, here is an example device tree:

https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/Documentation/devicetree/bindings/net/ti,dp83867.yaml?h=ti-linux-5.10.y

"ti,rx-internal-delay" or "ti,tx-internal-delay" can be used to adjust the RGMII delays and overwrite the strap values on startup (set as 3500 ps).

Register 0x32[1:0] is used to enable shift/align mode, and 0x86[7:0] is used to adjust TX/RX delays while in shift mode.

After setting the device tree and straps for 3.5ns, read 0x86[7:4] and 0x86[3:0] as '1101' to confirm 3.5ns delay has been set after power-up.

Please let me know if I can clarify further.

Thanks,
Evan

Hi Evan,

In DTSI we set 2.25ns thats why we are getting 0x0088 on 0xx86 registers.

Thanks

Sagar

Hi Sagar,

I understand. Is there any unexpected behavior or issue you are facing now?

Thank you,

Evan

Hi Evan,

Actually link is not getting up and we are seeing rx clk on 2.5MHz while tx clk on 125MHz. Not sure what to debug from SW perspective. Can you please let me know what is the function of Mirror EN strap? In my board is enable, do we need to disable it?

Thanks

Sagar

Hi Sagar,

Mirror enable is used if the MDI traces to the RJ-45 have been crossed to match the following port mapping:

If you don't expect this mapping is being used, please test with mirror mode disabled through strap or through writing 0x31[0] = '0'.

If this does not resolve your link issue, please share a register dump so I may review the PHY status and configuration.

Thank you,

Evan 

Hi Evan,

Thanks for your support. 1G is working now. we found Mirror enable strap on Mode 3 after changing to Mode1 it is start working. 

Thanks

Sagar

Hi Evan,

I have two more query on that-

1. Setting Mirror enable strap from mode 3 to mode 1solved my issue , just want to know since auto MDI/MDIx is there why it is depended on mirror enable strap?

2. As of now, on left side of RJ45 connector we have dual led Green and orange, which is connected to PHY as per below diagram, but i am not able to see any blinking on it. Please find RJ45 connector schematic as well.

I did one experiment-

i wrote on 0x0019 register with 0x4404 or 0x4440 so that led1 or led0 will be opposite of each other. After that left side dual led start blinking.

Please let me know how to resolve this issue.

Thanks

Sagar

Hi Evan,

If I changed the register value then it will reset to by defualt when system going to reset. Then how to write that value permanently in register?

Thanks

Sagar

Hi Sagar,

LED setting can be initialized in the driver / device tree for inverted polarity setting on startup - is this an acceptable work-around?

Thank you,

Evan

Hi Evan,

Are you sure do we need to reverse the polarity for one of the LEDs?

Thanks

Sagar

It's unclear to me whether it's needed, can you share more details about the PHY status without inverting polarity? Is link status up on both DP83867 and its link partner while you observe no LED activity?

Thank you,

Evan

Hi Evan,

I am using one DP83867 in my board and i am running a youtube video. Right led which is yellow is continuously blinking but left Led which is dual led is not blinking at all. And on 0x0019 we are getting 0x4444.

Thanks

Sagar

Hi Sagar,

The PHY status is unclear to me still, please read and share register value 0x1. If link status is up with 0x1[2] = '1', I expect the RJ-45 LED to turn on.

Thank you,

Evan

Hi Evan,

On 0x01 it is 0x769D.

Thanks

Sagar

Hi Sagar,

Please share the schematic so I may review (can email to e-mayhew@ti.com for private share).

Thank you,

Evan

Hi Evan,

PFA 

For LED0 and LED1 circuit - I already shared the detailed block diagram above

Thanks 

Sagar

Hi Sagar,

Please expect my feedback on this by EOD 5/29.

Thanks,

Evan

Hi Sagar,

Sorry, I am still unclear on the connection between the RJ-45 and LED_1/2.

Can the full PDF be shared, or a block diagram of the connection between PHY LED and RJ-45?

To restate the issue, mirror mode is disabled and link is working as expected, however the RJ-45 link LED remains off during link up (resolved through manually reversing polarity).

Thank you,

Evan

Hi Evan,

Please find detailed connection of LED 0 and 1 and datasheet of Rj45 connector.

https://www.we-online.com/components/products/datasheet/7499111614A.pdf

Note: Yellow Led is blinking which is right side of RJ45 and connected to LED2 but Dual led is not blinking.

Thanks

Sagar

Hi Sagar,

Please expect my feedback on this tomorrow.

Thanks,

Evan

Hi Sagar,

The strap configuration for LED0 and LED1 sets both LEDs as active high. Default function of LED_0 is general link status, and LED_1 is 1000BASE-T link status.

In the case of Gigabit link, both LED_0 and LED_1 will be driven high, resulting in no voltage difference between pins 15/16 of the RJ-45.

The solution in this case is to either disconnect LED_0 or LED_1 from RJ-45 to allow a voltage difference across a single LED, or to invert the polarity of either LED_0 or LED_1.

Please let me know if I can clarify further.

Thank you,

Evan

Hi Evan,

Is there any way to invert the polarity via hardware strap?

Thanks

Sagar

Hi Sagar,

LED polarity depends on strap mode of LED_0 / LED_1 pin:

Modes 1/2/3 = active high

Mode 4 = active low

LED_0 cannot support mode 4. LED_1 could be inverted with mode 4, however this is only recommended if the corresponding ANEG_SEL = 1 (100/1000M autoneg) and TX clock skew setting (Table 8-7) are acceptable for your design.

If this device is being used in a Linux environment, the simplest solution may be to configure LED polarity through driver / device tree on startup.

Thank you,

Evan