SN65DSI86: Question about SN65DSI86

Jimmy Huang

Part Number: SN65DSI86

Hello:

Problem description: During the production process of the production line, MIPI to EDP screen did not display. After powering off and turning on again, there is still no display.

Problem analysis:

1. The power on timing of SN65DSI86ZXHR meets the requirements of the specifications.

2. Measure the waveform of the external crystal oscillator at 26M. Does it meet the requirements? (Test DC, 1M Ω gear)

3. Design principle diagram of external clock

4. Crystal oscillator input, AC or DC. What is the minimum level that needs to be reached?

5. Signal waveform of C3335 replaced with 0 Ω resistance test

over 1 year ago

0 Vishesh Pithadiya over 1 year ago

TI__Mastermind 38150 points

Hey Jimmy,

Have you tried using the color bar patterns?

Have a look at this debugging guide: https://e2e.ti.com/support/interface-group/interface/f/interface-forum/945403/faq-sn65dsi86-sn65dsi86-black-screen-debugging-guide?tisearch=e2e-sitesearch&keymatch=sn65dsi86#

Additionally, use this spreadsheet to calculate the register values based off of the panel spec.

4382.SN65DSI86_PANEL_VIDEOREGISTER_CALC.xlsm

Let me know if you have questions.

Best,

Vishesh Pithadiya

0 Jimmy Huang over 1 year ago in reply to Vishesh Pithadiya

Genius 3515 points

Hello Vishesh：

This is a routine troubleshooting that cannot light up, but the customer now wants to know if there is a problem with the capacitor isolated AC input when using TCXO for the external clock, and if it is safer to change it to a series resistor with bias input?

The customer previously used SN65DSI86ZQER, and the circuit diagram is shown in the red box below,

Due to the discontinuation of this material, SN65DSI86ZXHR has been used instead. The circuit diagram is shown below. Please help confirm if it is reasonable. Thank you!!!

0 Vishesh Pithadiya over 1 year ago in reply to Jimmy Huang

TI__Mastermind 38150 points

Try removing the series cap and replacing it with a resistor.

This is the TI implementation from the DSI86-EVM

0 Jimmy Huang over 1 year ago in reply to Vishesh Pithadiya

Genius 3515 points

Hello Vishesh：

May I ask again

1. When using an external crystal oscillator, is the input signal AC or DC? How is the amplitude required?

2. The following image shows a waveform that has been replaced with 0 Ω. Could you please help troubleshoot if there is any problem?

3 If the external crystal oscillator is not attached and the software configuration uses an external crystal oscillator, can the chip work normally? Or will it try to lock frequency from MIPI CLK?

0 Vishesh Pithadiya over 1 year ago in reply to Jimmy Huang

TI__Mastermind 38150 points

Hey Jimmy,

Jimmy Huang said:
1. When using an external crystal oscillator, is the input signal AC or DC? How is the amplitude required?

The input signal should be DC coupled. The amplitudes require can be found in the datasheet:

Jimmy Huang said:
2. The following image shows a waveform that has been replaced with 0 Ω. Could you please help troubleshoot if there is any problem?

Looks like the frequency of the clock is 11.51Hz.

The required frequencies for the REFCLK are 12MHz, 19.2MHz, 26 MHz, 27 MHz, and 38.4MHz.

Jimmy Huang said:
3 If the external crystal oscillator is not attached and the software configuration uses an external crystal oscillator, can the chip work normally? Or will it try to lock frequency from MIPI CLK?

If there is no REFCLK and the software is configured for external clock the chip will not function normally. You will need to configure the chip to use the DSI clock. However, there are only certain frequencies of DSI clock that will work with the PLL so using REFCLK is recommended.

0 Jimmy Huang over 1 year ago in reply to Vishesh Pithadiya

Genius 3515 points

Hello Vishesh：

The customer is currently facing a problem: when there is an external crystal oscillator, the software 0A register is configured to fetch clk from the external crystal oscillator, and the 0A register is read as 0x84. However, the customer intentionally removed the external crystal oscillator on the hardware, and the software still writes 0A as 0x04, but the actual read is 0x05. Has this IC been automatically updated? Is this a normal phenomenon?

0 Vishesh Pithadiya over 1 year ago in reply to Jimmy Huang

TI__Mastermind 38150 points

The DSI86 shouldn't have an internal update for any registers other than the error registers this is not a normal phenomenon. What else is on the I2C line that could write to the DSI registers?

0 Jimmy Huang over 1 year ago in reply to Vishesh Pithadiya

Genius 3515 points

Hello Vishesh：

The customer has currently conducted the following black screen experiments

Prerequisite: The TI chip is connected to an external crystal oscillator of 26M, and the software 0X0A is configured with an external crystal oscillator of 0X04

1. Normal startup

Write 0X0A register as 0X04

Read 0X0A as 0X84

2. On the basis of step 1, measure the waveform of the external clock at the following positions

1) Under normal startup in step 1, when the oscilloscope probe points to the position shown in the picture, a black screen appears and the image is not displayed

2) When the oscilloscope probe is still in this position and not released, the device is powered off and restarted. The device goes black and does not display an image. The waveform of the crystal oscillator is normal. At this time, when grabbing the register log, it is found that the value of the 0X0A register has changed to 0X05, as shown in the following figure

Question:

1、Why does the oscilloscope probe contact the above test points and change the register value of 0x0A?

2、What is the basis for judging whether clk is normal with register 0x0A?

0 David (ASIC) Liu over 1 year ago in reply to Jimmy Huang

TI__Guru**** 176441 points

Hi,

Are they using a passive or an active probe to probe the oscillator input?

Below is the REF_CLK spec,

DSI86 will support 26MHz, and DP_PLL_LOCK bit of register 0x0A will go high if DSI86 detects a valid clock input.

Thanks

David

0 Jimmy Huang over 1 year ago in reply to David (ASIC) Liu

Genius 3515 points

Hello David：

At present, the hardware adapter chip uses an internal crystal oscillator, and the 0X0A register on the software is configured as 0X09. There is a problem that the XBL stage is not displayed, and there is no abnormality in printing the F0-F8 register. When the test mode is turned on, there is no color bar appearing in the XBL stage, but the kernel stage lights up normally. Can you help take a look at it？Thanks！！！

Fullscreen 2867.log.txt Download

Format: Log Type - Time(microsec) - Message - Optional Info
Log Type: B - Since Boot(Power On Reset),  D - Delta,  S - Statistic
S - QC_IMAGE_VERSION_STRING=BOOT.XF.4.1-00365-KAMORTALAZ-1
S - IMAGE_VARIANT_STRING=DivarPkgLAA
S - OEM_IMAGE_VERSION_STRING=qct192168097
S - Boot Interface: UFS
S - Secure Boot: Off
S - Boot Config @ 0x01b46070 = 0x00000049
S - JTAG ID @ 0x01b46130 = 0x002390e1
S - OEM ID @ 0x01b46138 = 0x00000000
S - Serial Number @ 0x01b46134 = 0x1075bb76
S - OEM Config Row 0 @ 0x01b441b8 = 0x0000000000000000
S - OEM Config Row 1 @ 0x01b441c0 = 0x0000000000000000
S - Feature Config Row 0 @ 0x01b441d0 = 0x005020001d600000
S - Feature Config Row 1 @ 0x01b441d8 = 0x0013000000020000
S - Core 0 Frequency, 1516 MHz
S - PBL Patch Ver: 1
S - PBL freq: 600 MHZ
D -      4502 - pbl_apps_init_timestamp
D -     58150 - bootable_media_detect_timestamp
D -      1453 - bl_elf_metadata_loading_timestamp
D -       677 - bl_hash_seg_auth_timestamp
D -      8441 - bl_elf_loadable_segment_loading_timestamp
D -      5778 - bl_elf_segs_hash_verify_timestamp
D -      7447 - bl_sec_hash_seg_auth_timestamp
D -      1161 - bl_sec_segs_hash_verify_timestamp
D -        28 - pbl_populate_shared_data_and_exit_timestamp
S -     87637 - PBL, End
B -    105520 - SBL1, Start (MPM timestamp = 113795)
B -    218596 - SBL1 BUILD @ 10:01:18 on Jun 12 2024
B -    224256 - usb: hs_phy_nondrive_start
B -    228273 - usb: hs_phy_nondrive_finish
D -      8527 - sbl1_hw_init
D -        12 - boot_flash_init
B -    333353 - UFS INQUIRY ID: YMTC    YMUS7B2TE1A2C1  3.7
B -    337789 - UFS Boot LUN: 1
D -       847 - Auth Metadata
D -    155103 - sbl1_xblconfig_init
D -         3 - sbl1_feature_config_init
D -         3 - boot_config_data_table_default_init
D -        17 - sbl1_ddr_set_default_params
B -    406926 - Using default CDT
D -      3917 - boot_config_data_table_init
B -    413764 - CDT Version:3,Platform ID:34,Major ID:1,Minor ID:0,Subtype:0
D -      9479 - sbl1_hw_platform_pre_ddr
D -      1717 - devcfg init
B -    431348 - PM: PM 0=0x8000028000000001:0x0
B -    431413 - PM: HARD_RESET by PS_HOLD
B -    471739 - PM: SET_VAL:Skip
B -    471910 - PM: PSI: b0x30_v0x0a
B -    478606 - PM: Device Init # SPMI Transn: 2726
B -    481834 - PM: Driver Init # SPMI Transn: 230
B -    483278 - PM: CHG Init # SPMI Transn: 0
D -     59654 - pmic XBL init
D -     10205 - vsense_railway_cpr init
D -     77751 - sbl1_hw_pre_ddr_init
D -         4 - boot_dload_handle_forced_dload_timeout
D -       490 - sbl1_load_ddr_training_data
D -      4970 - sbl1_ddr_set_params
B -    521150 - DSF version = 16.0, DSF RPM version = 8.0
B -    521189 - Manufacturer ID = 19, Device Type = 7
B -    526319 - Rank 0 size = 2048 MB, Rank 1 size = 2048 MB
B -    531109 - Max Frequency = 2092 MHz
B -    536508 - Row Hammer Check : DRAM supports unlimited MAC Value : MR24[OP2:0 = 0] & MR24[OP3 = 1] for CH0 & CS0
B -    545735 - Row Hammer Check : DRAM supports unlimited MAC Value : MR24[OP2:0 = 0] & MR24[OP3 = 1] for CH0 & CS1
D -     38370 - sbl1_ddr_init
B -    560685 - do_ddr_training, Start
B -    570945 - Bootup frequency set to 1555200
D -      7592 - do_ddr_training, Delta
D -     14556 - sbl1_do_ddr_training
D -         2 - sbl1_hand_control_to_devprog_ddr_or_ddi
B -    582041 - Pimem init cmd, entry
D -      9910 - Pimem init cmd, exit
D -     15630 - sbl1_post_ddr_init
D -        20 - sbl1_hw_init_secondary
B -    603660 - APDP Image Loaded, Start
D -      3207 - APDP Image Loaded, Delta - (0 Bytes)
D -         4 - boot_dload_dump_security_regions
B -    615696 - usb: UFS Serial - bd2971c6
D -      4364 - boot_dload_check
D -         2 - boot_cache_set_memory_barrier
D -         2 - boot_smem_debug_init
D -       306 - boot_smem_init
D -         5 - boot_smem_alloc_for_minidump
B -    636612 - PM: SMEM Chgr Info Write Success
D -      4008 - boot_smem_store_pon_status
D -        13 - sbl1_hw_platform_smem
D -       418 - boot_clock_init_rpm
D -         2 - boot_vsense_copy_to_smem
D -         1 - boot_share_flash_data
D -         9 - boot_populate_ram_partition_table
D -         9 - boot_populate_ddr_details_shared_table
D -         5 - sbl1_tlmm_init
D -         2 - sbl1_efs_handle_cookies
D -         2 - boot_apt_test
B -    678373 - OEM_MISC Image Loaded, Start
D -       938 - Auth Metadata
D -       310 - Segments hash check
D -      9136 - OEM_MISC Image Loaded, Delta - (8080 Bytes)
B -    690971 - QTI_MISC Image Loaded, Start
D -      5068 - QTI_MISC Image Loaded, Delta - (0 Bytes)
B -    702846 - PM: PM Total Mem Allocated: 1188
D -      5045 - sbl1_pm_aop_pre_init_wrapper
B -    709529 - RPM Image Loaded, Start
D -      1480 - Auth Metadata
D -      1701 - Segments hash check
D -     14889 - RPM Image Loaded, Delta - (220188 Bytes)
B -    727648 - QSEE Dev Config Image Loaded, Start
D -      1517 - Auth Metadata
D -       574 - Segments hash check
D -     12355 - QSEE Dev Config Image Loaded, Delta - (36396 Bytes)
B -    748777 - QSEE Image Loaded, Start
D -      5269 - Auth Metadata
D -     22771 - Segments hash check
D -     85092 - QSEE Image Loaded, Delta - (3454103 Bytes)
D -         6 - sbl1_hw_play_vibr
B -    842552 - SEC Image Loaded, Start
D -      2809 - SEC Image Loaded, Delta - (0 Bytes)
B -    848937 - QHEE Image Loaded, Start
D -      1533 - Auth Metadata
D -      3050 - Segments hash check
D -     13754 - QHEE Image Loaded, Delta - (388024 Bytes)
B -    866108 - STI Image Loaded, Start
D -      4937 - STI Image Loaded, Delta - (0 Bytes)
B -    875372 - APPSBL Image Loaded, Start
D -      1498 - Auth Metadata
D -     11348 - Segments hash check
D -     25234 - APPSBL Image Loaded, Delta - (2229248 Bytes)
D -         5 - sbl1_appsbl_arch_determination
B -    909929 - SBL1, End
D -    807872 - SBL1, Delta
S - Flash Throughput, 144000 KB/s  (6381065 Bytes,  44112 us)
S - DDR Frequency, 1555 MHz


UEFI Start     [ 1101]
 - 0x05FC01000 [ 1106] Sec.efi
ASLR        : ON
DEP         : ON (RTB)
Timer Delta : +9 mS
RAM Entry 0 : Base 0x0000000040000000  Size 0x000000003DA00000
RAM Entry 1 : Base 0x00000000C0000000  Size 0x0000000080000000
RAM Entry 2 : Base 0x0000000080000000  Size 0x0000000040000000
UART Buffer size set to 0x8000
UEFI Ver    : 5.0.240612.BOOT.XF.4.1-00365-KAMORTALAZ-1
Build Info  : 64b Jun 12 2024 10:01:45
Boot Device : UFS
PROD Mode   : TRUE
Retail      : TRUE
Module cannot re-initialize DAL module environment
UFS INQUIRY ID: YMTC    YMUS7B2TE1A2C1  3.7
UFS Boot LUN: 1
Embedded Images Supported and Commonlibs loaded
Read: NumHalfSectors 0x1, ReliableWriteCount 0x0
HW Wdog Setting from PCD : Disabled
PM0: 45,
UsbPwrCtrlLibConfig_GetHWInfo Hardware Info is not available
UsbPwrCtrlLib_Init Initialize Hardware Configuration Error[Device Error]
UsbConfigPortsQueryConnectionChange: Failed to open Power Control USB protocol Status =  (0xE)
MDPDataPartition: Failed to get partition info for block #0: Reason Unsupported
MDP_DataPartitionInit: splash PartitionFound=1
Setvariable returned Success
Ryan FsBlkBuffer = 31,31,31,31,0,0,0,Status= 0,EFI_SUCCESS =0,len=4096
Ryan ReadSsignChar Panel_Info =1111
display>>>Panel_Default_PowerUp pull up gpio102 for enable avdd start
display>>>Panel_Default_PowerUp pull up gpio102 for enable avdd stop
display>>>Panel_Default_PowerUp pull up gpio100 for enable avdd start
display>>>Panel_Default_PowerUp pull up gpio100 for enable avdd stop
display>>>Panel_Default_PowerUp pull up gpio35 for enable reset start
display>>>Panel_Default_PowerUp pull up gpio35 for enable reset stop
display>>>Panel_Default_PowerUp pull up gpio97 for enable avdd start
display>>>Panel_Default_PowerUp pull up gpio97 for enable avdd stop
display>>>EDP VCC 12V pull up gpio111 for enable avdd start
display>>>EDP VCC 12V pull up gpio111 for enable avdd stop
Ryan panel flag =0
RYAN DisplayDxe: edp init enter start
Ryan first edp_reg_init
DisplayDxe: I2C_INSTANCE_002=2!
Write addr:0x9 data:0x0 successs!, slave addr:0x2C
Write addr:0xA data:0x9 successs!, slave addr:0x2C
Write addr:0xD data:0x0 successs!, slave addr:0x2C
Write addr:0x10 data:0x26 successs!, slave addr:0x2C
Write addr:0x11 data:0x0 successs!, slave addr:0x2C
Write addr:0x12 data:0x5C successs!, slave addr:0x2C
Write addr:0x13 data:0x5C successs!, slave addr:0x2C
Write addr:0x20 data:0x80 successs!, slave addr:0x2C
Write addr:0x21 data:0x7 successs!, slave addr:0x2C
Write addr:0x22 data:0x0 successs!, slave addr:0x2C
Write addr:0x23 data:0x0 successs!, slave addr:0x2C
Write addr:0x24 data:0x38 successs!, slave addr:0x2C
Write addr:0x25 data:0x4 successs!, slave addr:0x2C
Write addr:0x2C data:0x14 successs!, slave addr:0x2C
Write addr:0x2D data:0x0 successs!, slave addr:0x2C
Write addr:0x30 data:0x8 successs!, slave addr:0x2C
Write addr:0x31 data:0x0 successs!, slave addr:0x2C
Write addr:0x34 data:0xA0 successs!, slave addr:0x2C
Write addr:0x36 data:0x1B successs!, slave addr:0x2C
Write addr:0x38 data:0x64 successs!, slave addr:0x2C
Write addr:0x3A data:0x14 successs!, slave addr:0x2C
Write addr:0x3C data:0x0 successs!, slave addr:0x2C
Write addr:0x3D data:0x0 successs!, slave addr:0x2C
Write addr:0x3E data:0x0 successs!, slave addr:0x2C
Write addr:0x5B data:0x1 successs!, slave addr:0x2C
Write addr:0x93 data:0x64 successs!, slave addr:0x2C
Write addr:0x94 data:0x81 successs!, slave addr:0x2C
Write addr:0x5C data:0x1 successs!, slave addr:0x2C
Write addr:0x5A data:0x5 successs!, slave addr:0x2C
Write addr:0xD data:0x1 successs!, slave addr:0x2C
Write addr:0x64 data:0x1 successs!, slave addr:0x2C
Write addr:0x74 data:0x0 successs!, slave addr:0x2C
Write addr:0x75 data:0x1 successs!, slave addr:0x2C
Write addr:0x76 data:0xA successs!, slave addr:0x2C
Write addr:0x77 data:0x1 successs!, slave addr:0x2C
Write addr:0x78 data:0x81 successs!, slave addr:0x2C
Write addr:0x96 data:0x1 successs!, slave addr:0x2C
Write addr:0x5A data:0xD successs!, slave addr:0x2C
RYAN DisplayDxe: edp init enter end
RYAN DisplayDxe: edp read enter start
Ryan edp_reg_read
DisplayDxe: I2C_INSTANCE_002=2!
First Read addr:0x9 rdbuf:0x0 successs!, slave addr:0x2C
First Read addr:0xA rdbuf:0x9 successs!, slave addr:0x2C
First Read addr:0xD rdbuf:0x1 successs!, slave addr:0x2C
First Read addr:0x10 rdbuf:0x26 successs!, slave addr:0x2C
First Read addr:0x11 rdbuf:0x0 successs!, slave addr:0x2C
First Read addr:0x12 rdbuf:0x5C successs!, slave addr:0x2C
First Read addr:0x13 rdbuf:0x5C successs!, slave addr:0x2C
First Read addr:0x20 rdbuf:0x80 successs!, slave addr:0x2C
First Read addr:0x21 rdbuf:0x7 successs!, slave addr:0x2C
First Read addr:0x22 rdbuf:0x0 successs!, slave addr:0x2C
First Read addr:0x23 rdbuf:0x0 successs!, slave addr:0x2C
First Read addr:0x24 rdbuf:0x38 successs!, slave addr:0x2C
First Read addr:0x25 rdbuf:0x4 successs!, slave addr:0x2C
First Read addr:0x2C rdbuf:0x14 successs!, slave addr:0x2C
First Read addr:0x2D rdbuf:0x0 successs!, slave addr:0x2C
First Read addr:0x30 rdbuf:0x8 successs!, slave addr:0x2C
First Read addr:0x31 rdbuf:0x0 successs!, slave addr:0x2C
First Read addr:0x34 rdbuf:0xA0 successs!, slave addr:0x2C
First Read addr:0x36 rdbuf:0x1B successs!, slave addr:0x2C
First Read addr:0x38 rdbuf:0x64 successs!, slave addr:0x2C
First Read addr:0x3A rdbuf:0x14 successs!, slave addr:0x2C
First Read addr:0x3C rdbuf:0x0 successs!, slave addr:0x2C
First Read addr:0x3D rdbuf:0x0 successs!, slave addr:0x2C
First Read addr:0x3E rdbuf:0x0 successs!, slave addr:0x2C
First Read addr:0x5B rdbuf:0x1 successs!, slave addr:0x2C
First Read addr:0x93 rdbuf:0x64 successs!, slave addr:0x2C
First Read addr:0x94 rdbuf:0x81 successs!, slave addr:0x2C
First Read addr:0xC2 rdbuf:0xF successs!, slave addr:0x2C
First Read addr:0x5A rdbuf:0xD successs!, slave addr:0x2C
First Read addr:0xD rdbuf:0x1 successs!, slave addr:0x2C
First Read addr:0x64 rdbuf:0x1 successs!, slave addr:0x2C
First Read addr:0x74 rdbuf:0x0 successs!, slave addr:0x2C
First Read addr:0x75 rdbuf:0x1 successs!, slave addr:0x2C
First Read addr:0x76 rdbuf:0xA successs!, slave addr:0x2C
First Read addr:0x77 rdbuf:0x1 successs!, slave addr:0x2C
First Read addr:0x78 rdbuf:0x81 successs!, slave addr:0x2C
First Read addr:0x96 rdbuf:0x1 successs!, slave addr:0x2C
First Read addr:0x5A rdbuf:0xD successs!, slave addr:0x2C
First Read addr:0xF0 rdbuf:0x0 successs!, slave addr:0x2C
First Read addr:0xF1 rdbuf:0x0 successs!, slave addr:0x2C
First Read addr:0xF2 rdbuf:0x0 successs!, slave addr:0x2C
First Read addr:0xF3 rdbuf:0x0 successs!, slave addr:0x2C
First Read addr:0xF4 rdbuf:0x0 successs!, slave addr:0x2C
First Read addr:0xF5 rdbuf:0x0 successs!, slave addr:0x2C
First Read addr:0xF6 rdbuf:0x0 successs!, slave addr:0x2C
First Read addr:0xF7 rdbuf:0x0 successs!, slave addr:0x2C
First Read addr:0xF8 rdbuf:0x0 successs!, slave addr:0x2C
First Read addr:0xFF rdbuf:0x0 successs!, slave addr:0x2C
RYAN DisplayDxe: edp read enter end
display>>>BOE EDP bl pull up gpio31 for enable avdd start
display>>>boe EDP bl pull up gpio31 for enable avdd stop
display>>> pull up gpio30 for enable led key

====Read panel id from ID's register,readsize=8===
00,00,00,00,00,00,00,00,
=====Get panel id from panellist=======
11,00,00,00,00,00,00,00,
++++++++++++
Dynamic-Detected panel Failed
DisplayDxe: Resolution 1920x1080 (1 intf)
LoadImageFromPartitionUsingGuid Failed: 14
MinidumpTALib:LoadImageFromPartition(mdcompress) failed: 0xNot Found
MinidumpTADxe: Minidump TA loading failed.
Disp init wait [ 2125]
DisplayDxe: Panel_Default_Brightness_Enable: Getting PMIC mode failed with error(4), power configuration Failed!
-----------------------------
Platform Init  [ 2370] BDS
UEFI Ver   : 5.0.240612.BOOT.XF.4.1-00365-KAMORTALAZ-1
Platform           : IDP
Chip Name          : DIVARQ_IOT
Chip Ver           : 1.0
Chip Serial Number : 0x1075BB76
-----------------------------
QcomChargerApp:: QcomChargerApp_Entry Charging is not supported. Exiting app. = Not Found
UEFI Total : 1289 ms
POST Time      [ 2390] OS Loader
[2396]Loader Build Info: May 15 2024 05:17:09
VB: Non-secure device: Security State: (0xF3F)
VB: RWDeviceState: Succeed using devinfo!
VB: Non-secure device: Security State: (0xF3F)
[2402]LinuxLoaderEntry secboot_flag=0
[2411]get getcode = 0
 [2413]Total DDR Size: 0x00000000FDA00000
[2413]boardidinit gpio success!
[2414]Channel GPIO3: nPhysical=1256, uMicroVolts=1255666, uPercent=43888, uCode=0x4B9A
[2414]Get adc convertvalue= :7
[2414]Get Board Id main_board_id_value= 31
[2414]Get Board Id boardidvalue= 0x1F
[2414]SunmiplatformInfo-odm_id_value   : 0x0
[2414]KeyPress:0, BootReason:0
[2414]Fastboot=0, Recovery:0
[2414]SilentBoot Mode:11
[2414]GetVmData: No Vm data present! Status = (0x3)
[2414]VM Hyp calls not present
[2415]Loading Image recovery_a Done : 1 ms, Image size : 4096 Bytes
[2417]Loading Image init_boot_a Done : 1 ms, Image size : 4096 Bytes
[2418]Booting from slot (_a)
[2418]Booting Into Mission Mode
[2419]Loading Image boot_a Done : 1 ms, Image size : 4096 Bytes
[2421]Load Image vbmeta_a total time: 1 ms
[2421]avb_vbmeta_image.c[2421]:[2421]207[2421]: ERROR: [2421]Hash does not match!
[2421]avb_slot_verify.c[2421]:[2421]782[2421]: ERROR: [2421]vbmeta_a[2421]: Error verifying vbmeta image: [2421]HASH_MISMATCH[2421]
[2422]Load Image vbmeta_system_a total time: 1 ms
[2645]Load Image boot_a total time: 203 ms
[2767]Load Image dtbo_a total time: 36 ms
[2793]Load Image init_boot_a total time: 18 ms
[3019]Load Image vendor_boot_a total time: 203 ms
[3033]ReadPersistentValue 0xE
[3034]Ftr OsVer:0x34000 SPL:0x2985
[3042]VB2: Authenticate complete! boot state is: orange
[3042]VB2: boot state: orange(1)
[3044]Silent Mode value: 11
[3044]Memory Base Address: 0x40000000
[3068]simon+++ SunmiBoardVariant = 0, DtSumVariant = 10001, DtSunmiSubtype = 0
[3068]simon+++ SunmiBoardVariant = 0, DtSumVariant = 10001, DtSunmiSubtype = 1
[3068]simon+++ SunmiBoardVariant = 0, DtSumVariant = 23, DtSunmiSubtype = 0
[3068]simon+++ SunmiBoardVariant = 0, DtSumVariant = 1F, DtSunmiSubtype = 1
[3071]Override DTB: GetBlkIOHandles failed loading user_dtbo!
[3332]Apply Overlay total time: 261 ms
[3333]LoadRawImage: ImageSize=1024
[3333]Loading Image Start : 3333 ms
[3333]Loading Image : 4096 8
[3333]Loading Image Done : 3333 ms
[3333]Total Image Read size : 1024 Bytes
[3333]Parse sn:D0P5126017
[3333]StrSN len: 13
[3333]LoadRawImage: ImageSize=4096
[3334]Loading Image Start : 3334 ms
[3334]Loading Image : 4096 42
[3334]Loading Image Done : 3334 ms
[3334]Total Image Read size : 4096 Bytes
[3334]Parse boardname:
[3334]RfIdNum =0 SocId =586 SubIoNum =0
[3334]ReadEthmacInfo StrEthmac: 1:A1:C9:5
[3334]eth not zero
[3335]ReadWifimacInfo StrWifimac: 1:A1:7D:4
[3335]wifi not zero
[3335]ReadBtmacInfo StrBtmac: 1:A1:C4:D
[3335]bt not zero
[3337]Error getting off mode charging info: Unsupported
[3338]Unable to get hw fence Config, Not Found
[3338]Offlining Memory Not Supported
[3338]Read Gpio93Value=1
[3338]Cmdline: video=vfb:640x400,bpp=32,memsize=3072000 firmware_class.path=/vendor/firmware bootconfig buildvariant=userdebug  meigset.eth.mac=1C:1A:1B:5C:99:E5 qca_cld3_wlan.mac=1C:1A:1B:77:D3:14 msm_drm.dsi_display0=qcom,mdss_dsi_sn65dsi86_1080p_video: rootw[3343]RAM Partitions
[3343]Add Base: 0x0000000040000000 Available Length: 0x000000003DA00000
[3343]Add Base: 0x00000000C0000000 Available Length: 0x0000000080000000
[3344]Add Base: 0x0000000080000000 Available Length: 0x0000000040000000
[3344]WARNING: Unsupported EFI_RAMPARTITION_PROTOCOL
[3364]ERROR: Ramdump mem reservation node size. Expected: 8, Actual: 16
[3384]PartialGoods for Multimedia: 0x1040
[3400]Subnode: qcom,mss is not present, ignore
[3400]PartialGoods Value: 0x30
[3400]Subnode: cpu@200 is not present, breaking loop
[3400]CPUType Mismatch for for Cluster[0]
[3401]Subnode: cpu@104 is not present, breaking loop
[3401]CPUType Mismatch for for Cluster[1]
[3402]CPUType Match for for Cluster[2]
[3402]Partial goods (cpu@100) enable-method property disabled
[3404][**zcool**] Partial goods (cpu@100) status property updated
[3404]Partial goods (cpu@101) enable-method property disabled
[3406][**zcool**] Partial goods (cpu@101) status property updated
[3406]Update Device Tree total time: 63 ms
[3407]
Shutting Down UEFI Boot Services: 3407 ms
Start EBS        [ 3407]
BDS: LogFs sync skipped, Unsupported
App Log Flush : 485 ms
Exit EBS        [ 3909] UEFI End

0 Vishesh Pithadiya over 1 year ago in reply to Jimmy Huang

TI__Mastermind 38150 points

Hey Jimmy,

Can you show a waveform of the refclk at the frequency needed by the DSI86?

Try running the following script. This is a script we use to test the color bar using the DSI86, this script is designed under the assumption that the refclk is 27MHz. If you are using a different frequency please tune accordingly.

Fullscreen 5315.1DP_4DSI_HBR_800x600_Color_Bar.xml Download

<aardvark>
    <configure i2c="1" spi="1" gpio="0" tpower="1" pullups="1"/>
    <i2c_bitrate khz="100"/>
    
  <i2c_write addr="0x2D" count="1" radix="16">5C 01</i2c_write> <sleep ms="10"/>

   <i2c_write addr="0x2D" count="1" radix="16">FF 07</i2c_write> <sleep ms="10"/>

======DUMP CFR======
   <i2c_write addr="0x2D" count="0" radix="16">16 </i2c_write> <sleep ms="10"/>

======Read======
    <i2c_read addr="0x2D" count="1" radix="16">00</i2c_read> <sleep ms="10"/>


   <i2c_write addr="0x2D" count="1" radix="16">16 01</i2c_write> <sleep ms="10"/>

   <i2c_write addr="0x2D" count="0" radix="16">16 </i2c_write> <sleep ms="10"/>

======Read======
    <i2c_read addr="0x2D" count="2" radix="16">00</i2c_read> <sleep ms="10"/>

  <i2c_write addr="0x2D" count="1" radix="16">FF 00</i2c_write> <sleep ms="10"/>


======Single 4 DSI lanes======

  <i2c_write addr="0x2D" count="1" radix="16">10 26 </i2c_write> <sleep ms="10"/>

======DSI CLK FREQ======

  <i2c_write addr="0x2D" count="0" radix="16">12 </i2c_write> <sleep ms="10"/>
   <i2c_read addr="0x2D" count="2" radix="16">00</i2c_read> <sleep ms="10"/>



======enhanced framing======

  <i2c_write addr="0x2D" count="1" radix="16">5A 04 </i2c_write> <sleep ms="10"/>


======ADDR 0x93 CFR======

   <i2c_write addr="0x2D" count="0" radix="16">93</i2c_write> <sleep ms="10"/>

======Read======
    <i2c_read addr="0x2D" count="6" radix="16">00</i2c_read> <sleep ms="10"/>

======Pre0dB 1 lanes no SSC======
   <i2c_write addr="0x2D" count="1" radix="16">93 10</i2c_write> <sleep ms="10"/>

======L0mV RBR======
   <i2c_write addr="0x2D" count="1" radix="16">94 80</i2c_write> <sleep ms="10"/>

======POST2 0dB ======
   <i2c_write addr="0x2D" count="1" radix="16">95 00</i2c_write> <sleep ms="10"/>

======PLL ENABLE======
   <i2c_write addr="0x2D" count="1" radix="16">0D 01</i2c_write> <sleep ms="10"/>
   <i2c_write addr="0x2D" count="0" radix="16">0A</i2c_write> <sleep ms="10"/>
   <i2c_read addr="0x2D" count="2" radix="16">00</i2c_read> <sleep ms="10"/>



======Semi-Auto TRAIN ======
   <i2c_write addr="0x2D" count="1" radix="16">96 0A</i2c_write> <sleep ms="20"/>


======ADDR 0x0A CFR======

   <i2c_write addr="0x2D" count="0" radix="16">96</i2c_write> <sleep ms="20"/>

======Read======
    <i2c_read addr="0x2D" count="1" radix="16">00</i2c_read> <sleep ms="10"/>

=====CHA_ACTIVE_LINE_LENGTH=======
    <i2c_write addr="0x2D" count="2" radix="16">20 00 04</i2c_write> <sleep ms="10"/>

=====CHA_VERTICAL_DISPLAY_SIZE=======
    <i2c_write addr="0x2D" count="2" radix="16">24 58 02</i2c_write> <sleep ms="10"/>

=====CHA_SYNC_DELAY=======
    <i2c_write addr="0x2D" count="2" radix="16">28 00 00</i2c_write> <sleep ms="10"/>

=====CHA_HSYNC_PULSE_WIDTH=======
    <i2c_write addr="0x2D" count="2" radix="16">2C 80 80</i2c_write> <sleep ms="10"/>

=====CHA_VSYNC_PULSE_WIDTH=======
    <i2c_write addr="0x2D" count="2" radix="16">30 04 80</i2c_write> <sleep ms="10"/>

=====CHA_HORIZONTAL_BACK_PORCH=======
    <i2c_write addr="0x2D" count="1" radix="16">34 28 </i2c_write> <sleep ms="10"/>

=====CHA_VERTICAL_BACK_PORCH=======
    <i2c_write addr="0x2D" count="1" radix="16">36 09</i2c_write> <sleep ms="10"/>

=====CHA_HORIZONTAL_FRONT_PORCH=======
    <i2c_write addr="0x2D" count="1" radix="16">38 28</i2c_write> <sleep ms="10"/>

=====CHA_VERTICAL_FRONT_PORCH=======
    <i2c_write addr="0x2D" count="1" radix="16">3A 01</i2c_write> <sleep ms="10"/>

=====DP_18BPP_EN =======
  <i2c_write addr="0x2D" count="1" radix="16">5B 01 </i2c_write> <sleep ms="100"/>

=====COLOR BAR =======
    <i2c_write addr="0x2D" count="1" radix="16">3C 10</i2c_write> <sleep ms="100"/>

======enhanced framing and Vstream enable======

  <i2c_write addr="0x2D" count="1" radix="16">5A 0C </i2c_write> <sleep ms="100"/>

======DUMP CFR======
    <i2c_write addr="0x2D" count="0" radix="16">20</i2c_write> <sleep ms="10"/>

======Read======
    <i2c_read addr="0x2D" count="32" radix="16">00</i2c_read> <sleep ms="10"/>



</aardvark>

0 Jimmy Huang over 1 year ago in reply to Vishesh Pithadiya

Genius 3515 points

Hello Vishesh:

Thank you for your feedback!!!

Customer has another question. If it is to be designed as an internal crystal oscillator, what is the design of this part?Thanks!!!

0 Vishesh Pithadiya over 1 year ago in reply to Jimmy Huang

TI__Mastermind 38150 points

Hey Jimmy,

The way to design this can be found in thedatasheet.

This step can be bypassed by I2C registers as well:

If GPIO selection of REFCLK or DACP/N frequency is not used, then software must program the REFCLK_FREQ, CHA_DSI_CLK_RANGE and CHB_DSI_CLK_RANGE through the I2C interface prior to issuing any DSI commands or packets to the SN65DSI86.

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SN65DSI86: Question about SN65DSI86