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Original question:

DP83867E: DP83867E not establish link when plugged into a computer

DP83867E: When is pin strapping required?

Navadeep Ganesh U
Prodigy 20 points
Part Number: DP83867E

Hi TI Team, 

We're suing the DP83867ERGZT in a custom board application interfacing with ZYNQ FPGA MIOs on Gigabit Ethernet MAC(GEM3). This is the only device in the system and LEDs are driven through LED_0 and LED_1 pins. Is there any hardware strapping required for the chip to respond over MDI bus? 

Protocol: RGMII
(default address should remain 0x00 is what I assume until any strapping is done)


  • 0
    TI__Mastermind 24998 points

    Hi Navadeep,

    For the PHY to respond over MDI bus with default auto-negotiation config, straps are not required.

    However, there are configurable RGMII TX/RX delays that can be strapped with pins GPIO_0, GPIO_1, LED_1, and LED_2.

    Adding strap options for these pins adds flexibility with meeting RGMII timing requirements, depending on delays from the trace layout and MAC internal delays. These delays can also be configured with register access or device tree in Linux.

    Thank you,

    Evan