DP83867IR: Inquiry Regarding Ethernet Chip Replacement - DP83865 to DP83867IR

Hi Pavithran G,

I'm glad to hear that you want to continue using a TI part! On the DP83867IR Product Page - Design Tools & Simulation tab, you can find the Design Review Checklist & Layout Checklist. If you want me to review your schematic and/or layout, please fill these out and return to me. Upon receipt of the checklists, review will take at most 5 business days.

Aside from reviewing your schematic, are there any specific features you are looking for in the DP83867?

Regards,

Alvaro 

Hi Alvaro,

Hereby I attached the design review checklist (SLVRBN1A_Checklist_Comment from GE Healthcare) for GMII mode.

1) kindly verify the attached excel sheet GMII mode_Clarification report and confirm the strapping connection are correct as per GMII mode.

2) Let me know any software tool is required to the configure this chip (GMII mode).

3) Does this chip require register configuration using (MDC and MDIO pin) or by strapping we can enable this chip.

Thanks,

Pavithran Gunasekaran

8203.GMII mode_Clarification report.xlsxSLVRBN1A_Checklist_Comment From GE Healthcare.xlsx

Hi Pavithran,

Thank you for returning the filled out checklist, I will get this back to you by EOD Wednesday June 19th at the absolute latest.

Just to confirm, you are using the 64-pin PAP package version of the DP83867 correct? This is the only one that supports GMII. 

Regards,

Alvaro

Hi Alvaro,

Yes, we are using 64-pin PAP package (DP83867).

Thanks,

Pavithran Gunasekaran

Hi Pavithran,

Thank you for confirming, as mentioned I will reply again with the reviewed schematic by end of day Wednesday June 19th.

Regards,

Alvaro

Hi Alvaro,

Thank you for your Feedback.

As per your comment, I have updated the checklist in column J. Please verify the updated design review checklist.

Thanks,

Pavithran Gunasekaran

8863.SLVRBN1A_Checklist_Comment From GE Healthcare_V2.xlsx

Hi Alvaro,

Thank you for your valuable feedback.

Could you please inform me if there is a development board available that features the DP83867IRPAP ethernet chip? Additionally, I would like to know how to obtain the board quickly.

Thanks

Pavithran G

Hi Pavithran,

We have our DP83867IRPAP-EVM available on our website.

Regards,

Alvaro

Hi Alvaro,

Based on your feedback, we modified our hardware connections, and now all checklists match the requirements. However, the chip is still not configured to GMII mode.

We monitored the RX_CLK at 2.5 MHz and CLK_OUT at 25 MHz using an oscilloscope (CRO).

Can you confirm if strapping alone is sufficient to configure the chip to GMII mode, or is additional register configuration required for this chip? 

Is there any one-to-one replacement for the DP83865 chip?

Thanks,

Pavithran Gunasekaran

Hi Pavithran,

CLKOUT is expected to be 25 MHz, but RX_CLK should be 125 MHz.

When you are measuring this signal, are you linked up at 1000Mbps?

Regards,

Alvaro

Hi Alvaro,

When measuring the signal, the ethernet cable was linked up at 1000Mbps.

Please share your Mail ID If possible.

Regards,

Pavithran Gunasekaran 

Hi Pavithran,

Email will not be shared on a public forum due to privacy. Please reach out to your local FAE.

Could you read Registers: 0x01-0x1F, 0x6E & 0x6F please? Note that 0x6e & 0x6F are extended registers, see this FAQ for more information.

Regards,

Alvaro

Hi Alvaro,

Now, RX_CLK is at 125 MHz, but there is no communication between the Ethernet chip and the PC as monitored using the Wireshark app.

Currently, the chip DP83867IRPAP-EVM is out of stock. Can you tell me when it will be available?

Thanks,

Pavithran Gunasekaran 

Hi Pavithran,

This is a functional forum, I cannot comment on when the PAPEVM will become available, please reach out to your FAE or Marketing contact.

I can still assist with debugging your GMII issue, how were you able to get the 125 MHz clock up? Could you provide a block diagram of your current set up and try activating different loopback modes to isolate the issue?

For example, a near end loopback would isolate the issue to the GMII Interface, such the SoC sends data to the PHY and the PHY returns it back to the SoC instead of sending it down the line. With this we can confirm if the packets sent equals the packets received.

Regards,

Alvaro

Hi Alvaro,

Thank you for your valuable feedback.

The Ethernet chip is now connected at 1000 Mbps, and we are receiving initial packets from the chip.

Currently, the CLKOUT pin is receiving a 25 MHz clock, but we need a 125 MHz clock.

How can we configure the CLKOUT pin to output a 125 MHz clock? Is it possible to achieve this through a hardware connection change?

Thanks,

Pavithran Gunasekaran

Hi Pavithran,

Apologies for the delay in response.

CLKOUT being 25 MHz is to be expected, by default it will output whatever XI input is. CLKOUT can be adjusted to different outputs in Register 0x0170.

Could I ask what the 125MHz is to be used for?

In giga-bit, the MDI (connector side) transmit clock is 125MHz. Read Reg 0xA to determine if you are the gigabit master or slave (this will help you determine if you want the transmit or receive clock for CLKOUT). 

Regards,

Alvaro

Hi Alvaro,

Could you please confirm if the connections for GLINK_STATUS_N and GLINK_ACTIVE_N from our existing design to the current design are correct as mentioned below? Currently, we are facing issues with link establishment.

Thanks,

Pavithran Gunasekaran 

Hi Pavirthran!

Apologies for not responding yesterday. Please find feedback below. Note that whether these LEDs are connected correctly or not, it should not affect the PHY's ability to link up. Link status can be checked by reading Reg 0x1.

Current Design:
LED_0 Active High, DS86 will light up

LED_2 Active High, DS88 will light up

Exiting Design:
LED_0 Active Low, has 2kPU

LED_2 Active Low, has 2kPU

Regards,

Alvaro