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TFP 410

Lior Glick
Prodigy 30 points
Other Parts Discussed in Thread: TFP410

Hi,

I am designing a board with a TFP410 connected to an FPGA.

The output of the TFP410 is connected to a Samsung 961E monitor.

The image is 1024*768 pixels.

 

The clock freq.  (IDCK+) is 50MHz.

Hsync and Vsync are active high for 256 clpcks , during which time DE is low.

Hsync, Vsync and DE change together on the rising edge of the clock.

The TFADJ resistor is 510 Ohm and connected to 3v3.

PD pin is connected to 3v3 ->Power UP

ISEL is low. ->I2C disabled

EDGE is high ->Rising Edge

BSEL is high -> 24 Bit

DKEN is low ->DSKEW disabled

CTL1 CTL2 CTL3 are low.

All the inputs to the TFP410 were sampled with a scope and appear to be OK.

The TFP410 outputs appear to be active and the clock is clean.

Our monitor remains black, so it seems that we are still missing some definition.

The TFP410 data sheet does not have much information concerning timing and does not describe any special requirements needed to initialize the monitor

Do you have any suggestions?

 

Thanks for your help.

Lior

lglick@iai.co.il

  • 0
    TI__Guru* 76130 points

    Hello Lior,

    Can you adjust your input frequency clock to 63.5MHz

    Regards.

  • 0
    TI__Mastermind 20985 points

    Hi Lior, you might want to view your panel datasheet to see its required timing.  It should specify the allowable horizontal and vertical periods, as well as clock frequency.  Many 1024x768 panels expect a nominal clock of 65MHz, and the tolerance varies.

    Thanks,
    RE

  • 0 in reply to Lior Glick
    TI__Mastermind 20985 points

    Inside that Word doc I found these 3 questions:
    1. Should I need to reverse the DE signal?
    2. What is the importance of 65 MHz clock frequency as long as the line and frame rates are satisfied.
    3. Does the monitor require a wake up command or are the Hsync and Vsync are enough?

    1. Polarity depends on panel specifications.
    2. Panels usually directly specify their required clock frequency range.  The frequency is also a function of frame size (resolution) and refresh rate.
    3. I don't know; you'll need to look at panel specs.

    Thanks,
    RE

  • 0 in reply to RE
    Prodigy 30 points

    Hi Ross

     

    1.The DE is input to TFP410 so how its can be depend on panel specifications?

    2.Is it possible that the TFP410 demand a delay between the active the HSYNC after active the DE?

    3.Do you have any time diagram that describe the SYNC&DE signals operation?

    Thanks,

    Lior

  • 0 in reply to Lior Glick
    TI__Mastermind 20985 points

    1. You're right.  To answer your question, your DE polarity is correct, where it's high for 1024 clocks for the active area.

    2. The TFP410 doesn't require any delay between when DE is changed, and setting HSYNC or VSYNC.  Changing DE will affect the transmitted data on the next clock, and that will be according to how HSYNC is currently set.

    3. There's no timing dependency between DE and the syncs.

    Thanks,
    RE

  • 0 in reply to Lior Glick
    TI__Mastermind 20985 points

    There's one other thing I noticed: the VSYNC period appears to be 50,738 clocks in the diagram.  With 1024+320 clocks per line, that corresponds to just 37 lines!  It seems you need >1,032,192 clocks per frame.

    Thanks,
    RE