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Tool/software:
Hello, due to the limited space on our PCB and the requirement for galvanic isolation, we would like to use an LVDS isolator for the Gigabit lanes. When connecting the CSI-2 lanes directly to the LVDS isolator, it seems that the LP states interfere with the transmission. Is there a way to either eliminate the LP state (as the continuous clock lane mode only supports it on the clock lane) --> (datalanes remain in HS mode?) or limit or reduce the LP voltage level? Thank you in advance.
HI Toralf,
We do not have any way to get rid of the LP state or limit/reduce the LP voltage.
Glenn