• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 33 subscribers
  • Views 204 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

TCAN4550: What is the minimum frequency clock required to run the CAN bus at 125Kbps?

TCAN4551-Q1: Jitter and not perfect 50% duty cycle when clocking - is this a problem for the TCAN4551?

Sandra Capri
Prodigy 20 points
Part Number: TCAN4551-Q1
Other Parts Discussed in Thread: TCAN4550,

Tool/software:

Hi,

As a followup to the previous question, we are generating a clock from a small RISC-V processor, and want to know if the clock will be sufficient for a TCAN4551.

Summary of the system:

  1. We are planning on running the SPI at 16MHz (the fastest our SoC will run the SPI).
  2. We are planning on running the CAN bus at 125Kbps.
  3. We are now using the TCAN4551 instead of the TCAN4550 because of the 1.8V support.

Here's an oscope trace of the clock we are currently generating:

As you can see, the clock has some jitter, you see the min at 21.05MHz, and the max at 21.98MHz.  The duty cycle varies a bit between 48.30% and 49.50%.  We are working on reducing the jitter as much as possible, but don't know if we can get much better than this.

Will this clock be sufficient for the TCAN 4551 at 125Kbps CAN speeds?

Thank you!

Sandra

  • 0
    TI__Mastermind 32970 points

    Hi Sandra,

    The ISO 11898-1 standard defines the tolerance of the node clock oscillator frequency around the nominal frequency to ensure compatible communication the nodes on the bus.  The tolerance (df) depends on the length of the time quantum, the segments of the bit time, and on the synchronization jump width.  The maximum difference between the node clock oscillators of any two nodes shall be 2 x df x fnom.

    The standard provides 5 equations that need to be met to determine the maximum tolerance df of the oscillator/clock frequency (fosc).  The bit rate of 125Kbps is important, but from a CAN perspective, this is just some integer number of time quanta assigned to the two phases of the bit in order to define the sample point.  So you will need to evaluate the clock from this perspective. 

    The good news is that slower bit rates have larger bit periods and therefore have a larger frequency tolerance if there are a sufficient number of time quanta.

    To your specific clock, the duty cycle doesn't concern me as much as the frequency.  The bit rate is made up of an integer number of time quanta, and therefore the clock frequency / bit rate must be an integer number.  Generally 20MHz is used in CAN which is what I think you are targeting which would lead to 160 tq per bit without a prescaler divider.  21MHz / 125KHz is still an integer value of 168 tq, but you are still providing a variable clock frequency between 21MHz and almost 22MHz, so this would likely lead to problems if other nodes had a more ideal clock.

    The TCAN4551-Q1 does not support a crystal, but you may need to use a 1.8V CMOS Compatible SMD Crystal Oscillator that produces a single-ended output but has the form factor of a standard crystal.  I'm not making any specific part recommendations, but the Abracon ASE3-20.000MHZ-K-T is an example such a device (datasheet link).

    Regards,

    Jonathan