SN65DPHY440SS: HS Data is not transferred on one Data-Channel

Tim Teuber

Part Number: SN65DPHY440SS

Tool/software:

Hi Team,

we are developing a application where we use the SN65DPHY440SS as a Redriver for a MIPI CSI-2 Interface with 2 Data-Channels and 1 Clock-Channel. We are currently facing the issue of Data Channel 0 not getting properly "redriven". Probing the signals with a oscilloscope, it looks like the redriver does not enter HS-Mode and only transfers the Low Speed Edges of the signal.

Following pictures show the Input (Yellow) and the Output (Blue) Signals of the SN65DPHY440SS

As you can see non of the HS Data gets transfered and the other parts of the signal also don't look right. Data Signal 1 as well as the Clock Signal are looking normal. I already tried enabling the HS Only Mode, as suggested by this forum post: https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1345522/faq-sn75dphy440ss-is-it-okay-to-swap-the-polarity-and-lane-order

Unfortunately this lead to the same results.

What could be the reason for this kind of behavior?

Best regards,

Tim

over 1 year ago

0 Vishesh Pithadiya over 1 year ago

TI__Mastermind 40110 points

Hey Tim,

Have a look at the following FAQ as well. Can you confirm that the DB0P/N LP TX is connected to an unterminated LP RX

e2e.ti.com/.../faq-sn65dphy440ss-what-is-the-design-constraint-for-dphy440-lane-0-when-using-in-a-mipi-csi-design

0 Tim Teuber over 1 year ago in reply to Vishesh Pithadiya

Intellectual 390 points

Hi Vishesh,

yes, the other side is connected to a CSI Interface on a Nvidia Jetson Nano. We also have a second CSI Interface that is symmetrical to the one that is not working. This Signal is also connected to the Jetson and the redriver is working correctly.

Regards,

Tim

0 Vishesh Pithadiya over 1 year ago in reply to Tim Teuber

TI__Mastermind 40110 points

Hey Tim,

I have asked the relevant engineers, and I will follow up as soon as I have an answer.

0 Vishesh Pithadiya over 1 year ago in reply to Vishesh Pithadiya

TI__Mastermind 40110 points

Hey Tim,

Can you send a block diagram of the system? I'm not sure I fully understand the connections.

Additionally can you show the inputs transitioning from LP1 state to the HS state. These is a specific sequence that needs to be followed.

0 Tim Teuber over 1 year ago in reply to Vishesh Pithadiya

Intellectual 390 points

Hi Vishesh,

here is a picture of the Positive and negative Channel of the Data Signal while transitioning from LP State to HS state:

0 Vishesh Pithadiya over 1 year ago in reply to Tim Teuber

TI__Mastermind 40110 points

Hey Tim,

Sorry for not being more clear. This is the sequence use to reach the high speed transmission state.

Can we confirm that this is happening?

If we are forcing the lanes into HS state we shouldn't be seeing an LP communication. When do you set the HS state with respect to the transmission of data?

Interface

Interface forum

SN65DPHY440SS: HS Data is not transferred on one Data-Channel