SN65LVDS4: Output current drive capability at VCC=1.8V

With a 1.2 V supply, AUC logic devices (e.g., SN74AUC1G125) just barely support 200 MHz. Their inputs are overvoltage tolerant, so you can use them to convert from the SN65LVDS4's output.

Hi Stephen,

Thank you for your questions on this device. TI has more recently release the DS90LVRA2 receiver, which is a 1.8V dual channel device that may be a better fit for your application. Please refer to this application note: Level Shift No More: Support Low Voltage I/O Signals Into a FPGA, Processor, or ASIC

Figure 17 (Receiver Voltage and Current Definitions) shows the definition of the receive output current (Io), with an absolute maximum of +/-12mA (not recommended to be designed to be used for extended periods). Figures 1 and 2 show the high level / low level output current if operating at VCC / VDD = 1.8V. This is plotted over high / low output current. Datasheet pg. 5 for the VOH and VOL specs show that these were specified operating at IOH = -4mA (VDD=1.8V) and IOL = 4mA (VDD=1.8V).

A level shifter can reduce the output to 1.2V. The SN74AVC1T45-Q1 supports up to 500Mbps, but the data rate will be lowered when translating down to 1.2V (240Mbps or 120 MHz). Is it possible for you to lower the data rate?

The ADC datasheet should have timing diagrams to show how DDR data transfer is related to the output clock. Here is a helpful application note to understand serial LVDS data capture: Understanding Serial LVDS Capture in High-Speed ADCs (ti.com).

Regards, Amy

Thank you Amy and Clemens for taking the time to reply.

Thanks for pointing out the 'Understanding Serial LVDS Capture' and  'Level Shift no More' app notes.

I have solutions for slower data rates and so I am particularly trying to solve for 400 Mbps (200 MHz clock, double rate data) and 1.2 V.

I have seen the DS90LVRA2 datasheet and I was concerned about the 7 ns propagation delay compared to 3 ns for the SN65LVDS4, and the change in propagation delay with temperature is poorer than the SN65LVDS4 which is very stable at 1.8 V. It does have the advantage of two receivers in the same package with channel to channel skew < 600 ps, and I may consider it instead, but still have the same question about output current performance at 8 mA, 1.8 V. There are no graphs of DS90LVRA2 output voltage level with current draw. 

I am aware of Figures 1 and 2 and the absolute maximum current, but want to know what happens at 8 mA with 1.8 V VCC.

Regards,

Stephen

For currents larger than the specified 4 mA, the output transistor might saturate, i.e., R_DS(on) might become large than the typical 31 Ω. How much is not predictable.

When the trace between the LVDS receiver and the FPGA input is short enough, you do not need 50 Ω termination. (But with a series resistor of about 27 Ω at the receiver's output pin, you would have source termination with about 50 Ω.)

Hi Stephen,

Let me check with our systems engineer on this to help you narrow down options. I will get back to you early next week. 

Regards, Amy

Hi Clemens, thanks for that insight. The 50 Ohm is a result of the resistor divider (75 & 150 Ohm) which I am considering at the driver output to reduce the 1.8 V down to 1.2 V, and is more of a co-incidental rather than intentional termination. I need to protect the FPGA input from overvoltage and by trimming the signal down a little with a divider it is something that might be more consistent in timing than adding a level translator to do the job. It does unfortunately increase the source impedance which could work against the signal in terms of noise susceptibility, particularly with so little margin down at those low voltage levels.
The concept works in the IBIS simulation, but I am not sure how believable that is at 8 mA.

Thanks Amy

Again, the output voltage at 8 mA is not guaranteed. If the trace is short (is it?), I would use 750 Ω and 1500 Ω.

Hi Stephen,

Our systems engineer ran some simulations, and determined either a 100:200 output divider or this level shifter: SN74AXCH1T45 data sheet, product information and support | TI.com could be options. The best option depends on factors such as like trace length between the receiver, FPGA, and load. 

Thank you, Amy

Hi Amy, the level shifter has too much propagation delay for 400MHz frequency. We may choose to compromise and reduce the data rate to 200 Mbps and use a lower performance FPGA bank that operates at 1.8 V.

Is there an IBIS model available for the DS90LVRA2, as none is linked on the product page?

With the SN65LVDS4, what does 10 MHz mean as a minimum recommended operating frequency? Does this mean it is unsuitable for DC coupled, static data?