SN75DP126: Signal Integrity failed

Hi Praveen,

Are you able to send the schematic/ layout of the design and the configuration used?

Its difficult to debug a compliance fail without the proper context in design and setup.

Have you tried increasing the output swing manually and captured the eye?

Additionally is the EQ properly tuned?

Please see the schematics. The EQ settings are default (0 dB).  I want to understand if the above eye mask overlapping can be occurred due to TI driver set at 0dB. if yes, does the eye diagram affects my display signal without any change in the output swing or register.

Hi,

What is the package of the resistor and capacitor on the main link outputs? They should be 0201. What's the value of the resistor on the main links? This should be no more that 0-3 Ohms.

Also try removing the ESD and see if that impacts the eye.

Yes it seems that the signal needs some equalization. Try manually setting the EQ and see if that improves the eye height.

Package used cap -0402, res-0603. The value of resistor is 0 ohm.  We don't t change the design, layout or firmware as we are in the last phase of project.  Could you please confirm, will there be any issue if I move ahead with the existing results?

Hi Praveen,

DisplayPort only requires that one of the voltage-swing and pre-emphasis settings pass compliance.

As long as you have a passing eye diagram and compliance report with any one of the pre-emphasis and voltage swing settings, I have no concerns moving forward.

In the future please use 0201 size passive components on the main link trace.

Hello,

As you can see above, the eye diagram and pre-emphasis is failing. I was expecting answers on below question  

1. Is this eye diagram failing because EQ setting by default is set at 0 db?

2. What will happen if we don't change the EQ settings or tune the voltage swing?

3. We don't want to do any deisgn changes. Could you please tell us if this will impacts the display performance?

4. Could you please check the results above and suggest your finding or root cause of failure ?

dummy_sch.pdf

Hello, please see the attached pdf schematics. There are 2 Dp ports (1 DP ports driven directly from CPU, 2nd DP port driven through TI redriver chip). Things to observe was the eye diagram and pre-emphasis level verification testing failed for TI redriver chip. please suggest your findings and observations and how this can be mitigated? Do we need to do any changes in the design or firmware? or there won't be any performance issues despite this eye diagram and pre-emphasis not passing compliance.

Hi Praveen,

praveen sah said:

Do we need to do any changes in the design or firmware? or there won't be any performance issues despite this eye diagram and pre-emphasis not passing compliance.

The pre-emphasis tests are all relative. Meaning that pre-emphasis level 1 must be 0.8 dB greater than pre-emphasis level 0, pre-emphasis level 2 must be 0.8dB greater than pre-emphasis level 1, etc..

failing this test is low risk.

The eye-diagram test is not low risk and there must be a passing eye to avoid future interoperability issues. This will require debug and potentially editing the firmware. There are a few ways to improve your eye diagram test. This test must be passed.

1) improve EQ

2) change output swing settings

3) have the part participate in link training.

What is the compliance setup you are using?

Hi,

I'm closing this thread due to inactivity

Hello,

Thanks for your inputs. As i can understand that the results are not acceptable and we need to improve the EQ or change output swings to pass the eye diagram test.

Yes this is correct. Do you need any help gathering this data/ tuning the device?