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Tool/software:
We use two DS16EV5110A to drive DVI 2560*1600@60Hz with D0~D5 data, however there is no phenomenon on the PC side with 2560*1600@60Hz edid parameter.
1) PC is equipped with a GPU to support higher resolution;
2)Cable can support higher resolution than 2560*1600@60Hz;
3)Modify EDID to 1920*1080@60Hz , PC can recognize the signal,we think it works with d0~d2 data.
Attached is a schematic diagram ,thanks a lot!
Hi,
Is it possible to share the schematics as PDFs? Unfortunately the images are low resolution and are hard to view. You can send them over private message if you would prefer not to post them.
I can't tell from your schematic image, but I'm wondering if you have EN and SD pin connected.
Thanks,
Drew
Hi Zhen,
I believe I received your schematic from the TI field team.
It appears you have EN/SD connected similar to the block diagram below.
Is it possible to measure and confirm that EN on U73 is getting pulled HIGH when testing 2560*1600@60Hz?
Thanks,
Drew
Hi,Drew~
1.We measure and confirm U70-EN/U70-SD/U73-EN keep low level when testing 2048*2048@60Hz;
2.We measure and confirm U70-EN/U70-SD/U73-EN geting pulled high level when testing 1920*1080@60Hz;
3.Whether the SMbus needs to be open when dual link?
TKS.
Additional notes:
1.There are two E2PROM-M24C02 U46&U85 to store EDID , we only use U46 in application and remove U48.
2.We modify the circuit to keep SMbus(CS/SDA/CLK)open,however it does not work.
Hi Zhen,
As an experiment, if you force the EN high for U70/U73, will this enable 2048*2048@60Hz?
I wouldn't expect that SMBus need to be disabled
Also, I'm not as familiar with DVI. Does the clock signal have a different rate or amplitude for dual link?
You might also try lowering the SD_OFF/ON thresholds. Could you try option 1 (55mV SD_ON)?
Thanks,
Drew
We think PC recognizes EDID configed with 2048*2048@60Hz ,it will output 6 data&1clk data to two DS16EV5110A .
Do other customers have DVI dual link application experience ?
Hi Zhen,
Did you try to force EN high for U70/U73 to see if this enables dual link? I'd like to confirm that the issue you're observing with dual link is related to device EN. Device EN needs to be high for the device to work, and your previous experiment that showed that for some reason, EN was not high for your dual link test.
This is an older device, so I don't have much first hand experience with other customers designing in dual link. However, looking over our E2E forum, I see we have confirmed that we support dual link over the history of this device. Additionally, the fact that there is a block diagram for dual link in the data sheet strongly suggests that dual link is supported.
Thanks,
Drew
Hi Drew,
1) I‘m so sorry e missed a detail,what cable we uesd only support 2K DVI→HDMI,when DVI→HDMI support 1080P.
HDMI→DVI cable only support 1080P ,after change to DVI→DVI cable , 2048*2048@60Hz recognizes OK.
2)However there is another issue to solve,DVI clock only feed to DS16EV5110_A when using dual device,TFP401_A can decode hsync/vsync/den/data correctly,there is no sync signal and incorrect data from TFP401_B, so is there any idea?
Thanks.
Hi Zhen,
I'm checking in with a colleague on this, and expect to have an update tomorrow.
Thanks,
Drew
Hi Zhen,
The TFP401 will need the clock signal to time the incoming HDMI signal properly. This is why we see path A work and path B fail. The HDMI clock is a discrete clock lane and no clock information is embedded in HDMI data. This is why having the HDMI clock provided to the part is necessary.
Hi Zhen,
Yes, this is the best way to address the missing clock for the TFP401 in path B. This added connection will add reflections to the OCLK signal. Make sure the clock still meets the electrical requirements of the TFP401.
Are you able to reduce the resolution so only one TFP401 is required?
A single TFP401 can go up to WUXGA @ 60Hz. If this resolution is acceptable then only one TFP401 is required and this breakout is not necessary.