DS90UB948-Q1: ds90ub948 iic no ack at back channel 20Mbps

Good afternoon,

I have a few questions:

1. Is this being tested on custom boards or on TI EVMs?

2. Is video stable? If not, could you also probe the LOCK pin on the 948 to see if there are LOCK drops


3. If this link is unstable at higher back-channel speeds, this could imply potential CRC errors.

         - You provided a register dump for the 948, can you also provide a full register dump for the 947 SER
         - Check the back channel CRC error count (0xA - 0xB) and other related registers
         

Best regards,
Ikram

Hi,

   Thanks for your reply.

1、on custom boards.

2、at 20Mbps LOCK sometimes drops

3、yes，crc errors register as below.

pic 1. at 5Mbps, no crc error count.

pic 2, at 20Mbps ,crc error count 0xff.

Hello,

Since there are back channel CRC errors, and LOCK drops, there could be an issue with signal integrity. Were these boards validated before?

1. Can you please try Internal Pattern Generator from the 949? This would help to verify whether the 949 input is causing the error. You can use the ALP GUI PatGen tab for this

       
2. Do you know if the boards meet the channel specifications and signal integrity? Are you using coax or STP connector?


3. Are the mode selections and schematic matching the datasheet? 


Best regards,
Ikram

hello,

1、947 internal Pattern causes error ? the answer is yes.

2、we use coax connector. I do not know about channel specifications and signal integrity.I wiill check later.

3、the mode selections and schematic match datasheet.

Besides. I test BISTbetween 947 and 948 also have crc errors on back channel .

Hello,

Can you also please try using the MAP tool on ALP. https://www.ti.com/lit/ug/snlu243/snlu243.pdf?ts=1729892117182&ref_url=https%253A%252F%252Fwww.google.com%252F

Also, from register 0x5A DUAL_STS on the 947, it looks like the device is set for single-link mode. Is that as expected? What is your video PCLK?

- Ikram

hi, Ikram

We don't have USB2ANY device,but we have a eye diagram measurement .the test result is in the pdf.DS90UB948-FPD LINK.pdf

The device is set for single-link mode as we expected.the pclk 26.2Mhz (800x480)

Hello,

You can also connect using Aardvark I2C connection to use ALP and MAP tool for this.

Please give me 1-2 days to come back to you regarding potential next steps.

Best regards,
Ikram

Hello,

With the Pattern Generator, is there still any flickering or black screen, LOCK drops, and CRC errors? Or does it occur both with the SER pattern generator and with LVDS input to 947?

And for these custom designs, how many boards were tested? And how many show this issue?

- Ikram