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Original question:

SN65DSI83: The rise and fall times of REFCLK for SN65DSI83

SN65DSI83: Tr=4.6ns, Tf=3.6nS, any possible risks?

Ken Zhang
Expert 3645 points
Part Number: SN65DSI83


Tool/software:

Hi,

The rise and fall times of REFCLK for SN65DSI83 in a my account are 4.6nS and 3.5nS,separately, are longer than that listed in datasheet, would  you like kindly check if any possible risks?

The rise and fall time waveform of REFCLK of SN65DSI83 is tested from 10% to 90% by oscilloscope.

tr/ tf  min 100ps max 1ns is listed in SN65DSI83 datasheet.

  • 0
    TI__Mastermind 42811 points

    Hi Ken,

    Yes this rise and fall time is too slow for the REFCLK implementation.

    Try reducing the size of the capacitor C49 to speed up the edges.

  • 0 in reply to Vishesh Pithadiya
    TI__Expert 3645 points

    Veshesh

    Customer had used this circuit in its last generation product in which the rise and fall time was shown as above . Now need you help to check what specific risks the slow rise and fall may be caused, then customer will evaluate if they must change the design in coming project.

  • +1 in reply to Ken Zhang
    TI__Mastermind 42811 points

    Hi Ken,

    Even though the customer did not see any issues with the device when using the out of specification REF clock. This does not mean that there will not be any issues in the future. Please advise the customer to adjust the circuit to meet the requirements of our device. The risk associated is that the clock edges may be too slow for the PLL to properly detect. This would mean that the LVDS clock would be improperly timed resulting in failure of the DSI to LVDS bridge.