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DP83867IR: Ethernet Test Mode 1 outputs only on channel A, unstable 1GBps link

Part Number: DP83867IR

Tool/software:

Hi,

we have problems with 1GBps link, it works only with short ethernet cables. This may be related to our board design, which is under review. Hints are always appreciated!

Meanwhile, we did dome tests regarding ethernet qualification and if we activate test mode 1, we can see only a signal on channel A instead of all channels. Whatever we do with register 0x25, the test signal is only on channel A. This is how we configure the chip (SJA1110 is the chip to which the DP83867IR is connected via RGMII):

// Test mode 1 on all channels
PHY_SJA1110_SMI_write(PHY_SJA1110_ADDRESS_DP83867IR, 0x001F, 0x8000);
// 1GBit/s full duplex, AN off
PHY_SJA1110_SMI_write(PHY_SJA1110_ADDRESS_DP83867IR, 0x0000, 0x0140);
PHY_SJA1110_SMI_write(PHY_SJA1110_ADDRESS_DP83867IR, 0x0009, 0x3B00);
//PHY_SJA1110_SMI_write(PHY_SJA1110_ADDRESS_DP83867IR, 0x0025, 0x480); // all channels
//PHY_SJA1110_SMI_write(PHY_SJA1110_ADDRESS_DP83867IR, 0x0025, 0x400); // A
//PHY_SJA1110_SMI_write(PHY_SJA1110_ADDRESS_DP83867IR, 0x0025, 0x420); // B
//PHY_SJA1110_SMI_write(PHY_SJA1110_ADDRESS_DP83867IR, 0x0025, 0x440); // C
PHY_SJA1110_SMI_write(PHY_SJA1110_ADDRESS_DP83867IR, 0x0025, 0x460); // D
PHY_SJA1110_SMI_write(PHY_SJA1110_ADDRESS_DP83867IR, 0x01D5, 0xF508);
PHY_SJA1110_SMI_write(PHY_SJA1110_ADDRESS_DP83867IR, 0x001F, 0x4000);

Shouldn't there be a signal on channels A,B,C,D in test mode 1? I checked that there is no shortcut on the other channels, does not seem so.

Thanks and best regards, Rainer

  • Ok, register access to 0x25 seems only possible idirectly and register 0x1d5 seems not to be needed. Now the test signal comes on all 4 channels.

    However, the link is unstable, I played around with the impedance settings in register 0x170 but no success.

    In the test mode 1, some signals get "too big" while others fit perfectly. I guess, I need to read the IEEE description of the test to understand what is tested here and how to interpret the results...

  • Hi Rainer!

    Glad to hear that you found the Extended Register Space Access to solve the Reg 0x25 issue. Indirect Register access will be needed for all registers except for Reg 0x0-0x1F. Reg 0x170 and Reg 0x1D5 also need to be accessed indirectly. Reg 0x1D5 is needed for running compliance tests, this may resolve the signals getting "too big". Reg 0x170 adjusts the impedance on the MAC signals, the MAC interface is independent from the MDI (cable side), this will not affect link status or cable reach.

    Compliance aside, I want to focus on the main short cable issue. Could you provide more details to this issue?

    1. What is the maximum length cable that is working
    2. How many boards are affected with this issue
    3. Does this occur with multiple different link partners

    For Board Design, please see our DP83867 Design Review Checklist and DP838xx Industrial Layout Checklist, which can both be found under the Design Tools & Simulation tab of the DP83867 Product Page

    Regards,

    Alvaro

  • Good morning Alvaro,

    thank you for the information! It was possible to solve the unstable 1GBps link issue by switching the DP83867IR into "normal" mode.


    I will check if the ethernet qualification passes with the setting in register 0x1d5. Ethernet-Tester is not always available., so this may take some days.

    Best regards, Rainer

  • Hi

    Unfortuately, the test mode 1 did not pass, the PeakMagA and PeakMagB were quite a bit (~650mV) below the expected values (~745mV).

    Should the VoC setting of  0xF508 to register 0x01DF help on this? Any idea, why the peak voltages are so low? They are low on all 4 channels.

    Best regards, Rainer

  • Hi Rainer!

    Glad to hear the unstable link issue was resolved, what mode was the DP83867 in before you switched it into "Normal" mode?

    For Peak A & B, yes, Reg 0x1D5 = 0xF508 should resolve this. Please confirm you are using the script mentioned in the FAQ linked below.

    [FAQ]-dp83867e-1000base-t-ethernet-compliance-register-script

    Regards,

    Alvaro

  • Good morning Alvaro,

    unfortunately, peak A&B are still 100mV too small (says the ethernet compliance testing device while waveforms are fine) , I cannot tell that the setting in registter 0x1d5  had a significant influence on the peak values.
    Can you confirm that the expected peak A&B are around 750mV? Our ethernet compliance tester device is filled with lots of scripts and a little mess to use.

    Regarding the "normal power mode": I got this information from
    https://www.ti.com/lit/an/snla246c/snla246c.pdf?ts=1730306792278

    page 19. No idea what is meant with "lower power mode", we use the phy just as it is powered up, not disabling anything. But this setting clearly resolved the issue of no link with a long/suboptimal ethernet cable.

    Is somewhere documentation available for these registers?

    Best regards, Rainer

  • Hi Rainer,

    Thank you for pointing me to the document you were referring to, funny enough that is the same register I was telling you about for the compliance test!

    Reg 0x1D5 changes the swing level of the output signal on the MDI side of the PHY (cable side). By default, the swing is at a lower level, which was referred to as Low Power Mode. Reg 0x1D5 = 0xF508 increases the swing level, which should be visible if measuring on a scope (even with the Compliance Test Mode 1 Signal).

    Please remember that Reg 0x1D5 is an extended register and cannot be written to directly.

    Just to confirm, your long cable issue is resolved, do you still need to run the compliance test or was the compliance test a form of debugging the issue?

    Regards,

    Alvaro