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Original question:

DS90UB962-Q1: No camera picture output

DS90UB962-Q1: Cann't show camera with UB933.

robin mu
Prodigy 30 points
Part Number: DS90UB962-Q1

Tool/software:

We use UB962 and UB933, write registers as below:

ds90ub962_933_write_reg(DS90UB962_ADDR, 0x4C, 0x01); // Set up Port0
ds90ub962_933_write_reg(DS90UB962_ADDR, 0x70, 0x1F);
ds90ub962_933_write_reg(DS90UB962_ADDR, 0x6D, 0x7F); // RAW10 Mode
ds90ub962_933_write_reg(DS90UB962_ADDR, 0x6E, 0xAA);
ds90ub962_933_write_reg(DS90UB962_ADDR, 0x5C, 0xBA); //933 alias id
ds90ub962_933_write_reg(DS90UB962_ADDR, 0x7C, 0x81);
ds90ub962_933_write_reg(DS90UB962_ADDR, 0x10, 0x91);
ds90ub962_933_write_reg(DS90UB962_ADDR, 0x58, 0x58); //I2C Pass-Through Enabled
ds90ub962_933_write_reg(DS90UB962_ADDR, 0x19, 0x0D); //FS_HIGH_TIME_1
ds90ub962_933_write_reg(DS90UB962_ADDR, 0x1A, 0x04); //FS_HIGH_TIME_0
ds90ub962_933_write_reg(DS90UB962_ADDR, 0x1B, 0x75); //FS_LOW_TIME_1
ds90ub962_933_write_reg(DS90UB962_ADDR, 0x1C, 0x2E); //FS_LOW_TIME_0
ds90ub962_933_write_reg(DS90UB962_ADDR, 0x18, 0x01);
ds90ub962_933_write_reg(DS90UB962_ADDR, 0x20, 0x00);
ds90ub962_933_write_reg(DS90UB962_ADDR, 0x32, 0x01);
ds90ub962_933_write_reg(DS90UB962_ADDR, 0x33, 0x01);


ds90ub962_933_write_reg(DS90UB933_ADDR, 0x06, 0x60); //DES ID
ds90ub962_933_write_reg(DS90UB933_ADDR, 0x07, 0x60); //DES Alias
ds90ub962_933_write_reg(DS90UB933_ADDR, 0x08, 0xBE);
ds90ub962_933_write_reg(DS90UB933_ADDR, 0x09, 0xBE);
ds90ub962_933_write_reg(DS90UB933_ADDR, 0x0D, 0x55);
ds90ub962_933_write_reg(DS90UB933_ADDR, 0x0F, 0x02);
ds90ub962_933_write_reg(DS90UB933_ADDR, 0x10, 0x17);
ds90ub962_933_write_reg(DS90UB933_ADDR, 0x11, 0x21);
ds90ub962_933_write_reg(DS90UB933_ADDR, 0x12, 0x21);
ds90ub962_933_write_reg(DS90UB933_ADDR, 0x1E, 0x02);
ds90ub962_933_write_reg(DS90UB933_ADDR, 0x35, 0x0A);
ds90ub962_933_write_reg(DS90UB933_ADDR, 0x05, 0x35);
ds90ub962_933_write_reg(DS90UB933_ADDR, 0x10, 0x17);
ds90ub962_933_write_reg(DS90UB933_ADDR, 0x0D, 0x11);
ds90ub962_933_write_reg(DS90UB933_ADDR, 0x0D, 0x15);
ds90ub962_933_write_reg(DS90UB933_ADDR, 0x03, 0xE7);
ds90ub962_933_write_reg(DS90UB933_ADDR, 0x03, 0xC7);

But cann't show camera, and checked the register 4D is 0x13, please help check, thanks!

  • 0
    TI__Guru** 107810 points

    Hello Robin,

    Can you provide register dump from the UB960 for the used RX port?

    Can you provide schematic for both devices?

    Did you measure the CSI-2 TX port on the UB960? Do you have any data there?

    What is the data type and resolution, frame rate coming from the image sensor into the UB933?

    Do you see the same behavior if you connect the SER/Camera to any other RX port on the UB960?

    I have reviewed the provided sequence and here are some comments along with your lines:

    ds90ub962_933_write_reg(DS90UB962_ADDR, 0x4C, 0x01); // Set up Port0
    ds90ub962_933_write_reg(DS90UB962_ADDR, 0x70, 0x1F); YUV422 10-bit data
    ds90ub962_933_write_reg(DS90UB962_ADDR, 0x6D, 0x7F); // RAW10 Mode
    ds90ub962_933_write_reg(DS90UB962_ADDR, 0x6E, 0xAA); Frame Sync over BC GPIO 0,1
    ds90ub962_933_write_reg(DS90UB962_ADDR, 0x5C, 0xBA); //933 alias id
    ds90ub962_933_write_reg(DS90UB962_ADDR, 0x7C, 0x81); Are you sure Frame Valid is low for the duration of the video frame?!
    ds90ub962_933_write_reg(DS90UB962_ADDR, 0x10, 0x91);
    ds90ub962_933_write_reg(DS90UB962_ADDR, 0x58, 0x58); //I2C Pass-Through Enabled
    ds90ub962_933_write_reg(DS90UB962_ADDR, 0x19, 0x0D); //FS_HIGH_TIME_1
    ds90ub962_933_write_reg(DS90UB962_ADDR, 0x1A, 0x04); //FS_HIGH_TIME_0
    ds90ub962_933_write_reg(DS90UB962_ADDR, 0x1B, 0x75); //FS_LOW_TIME_1
    ds90ub962_933_write_reg(DS90UB962_ADDR, 0x1C, 0x2E); //FS_LOW_TIME_0
    ds90ub962_933_write_reg(DS90UB962_ADDR, 0x18, 0x01);
    ds90ub962_933_write_reg(DS90UB962_ADDR, 0x20, 0x00);
    ds90ub962_933_write_reg(DS90UB962_ADDR, 0x32, 0x01);
    ds90ub962_933_write_reg(DS90UB962_ADDR, 0x33, 0x01);


    ds90ub962_933_write_reg(DS90UB933_ADDR, 0x06, 0x60); //DES ID
    ds90ub962_933_write_reg(DS90UB933_ADDR, 0x07, 0x60); //DES Alias
    ds90ub962_933_write_reg(DS90UB933_ADDR, 0x08, 0xBE);
    ds90ub962_933_write_reg(DS90UB933_ADDR, 0x09, 0xBE);
    ds90ub962_933_write_reg(DS90UB933_ADDR, 0x0D, 0x55); default value
    ds90ub962_933_write_reg(DS90UB933_ADDR, 0x0F, 0x02);
    ds90ub962_933_write_reg(DS90UB933_ADDR, 0x10, 0x17); default value
    ds90ub962_933_write_reg(DS90UB933_ADDR, 0x11, 0x21); Why reducing the default?
    ds90ub962_933_write_reg(DS90UB933_ADDR, 0x12, 0x21); Why reducing the default?
    ds90ub962_933_write_reg(DS90UB933_ADDR, 0x1E, 0x02); Why reducing the default?
    ds90ub962_933_write_reg(DS90UB933_ADDR, 0x35, 0x0A); If used, must be configured after reg 0x03
    ds90ub962_933_write_reg(DS90UB933_ADDR, 0x05, 0x35);
    ds90ub962_933_write_reg(DS90UB933_ADDR, 0x10, 0x17); Once again writing to default
    ds90ub962_933_write_reg(DS90UB933_ADDR, 0x0D, 0x11);
    ds90ub962_933_write_reg(DS90UB933_ADDR, 0x0D, 0x15);
    ds90ub962_933_write_reg(DS90UB933_ADDR, 0x03, 0xE7);
    ds90ub962_933_write_reg(DS90UB933_ADDR, 0x03, 0xC7); [1] override CLK to PLL mode. Allows selection through reg 0x35.

  • 0 in reply to Hamzeh Jaradat
    Prodigy 30 points

    Hi Hamzeh，

    Thank you for the comments，I can show the camera， but there has green screen like this：

    Currently the resolution is 1024*600 and the data type is YUV422 10bit, do you have any idea what caused this ?

  • 0 in reply to robin mu
    TI__Guru** 107810 points

    Hello Robin,

    Are you sure you are using YUV422 10-bit data type? because in the 960 reg 0x7C you are setting bits [7:6] to 10, which means you are not processing all 10-bits but only the upper 8-bits. Please change this to 00 and see if that changes your output picture.

    Also, on the 933 schematic, make sure to pull GPO2 to GND with a minimum 40kΩ resistor to ensure GPO2=LOW when PDB transitions from LOW to HIGH

    Finally, please refer to UB960 datasheet section "7.4.12 RAW Mode LV / FV Controls" and make sure follow the instructions and timing explained there.

  • 0 in reply to Hamzeh Jaradat
    Prodigy 30 points

    Hi Hamzeh,

    I already changed reg 0x7C to 00 before the green screen output.

    I have read the section "7.4.12 RAW Mode LV / FV Controls" , but i cann't understand, can you give me a suggestion to set FV_MIN_TIME?

    and if the data type is YUV422 10BIT coming from UB933, Can UB962 change it to YUV422 8BIT?

  • 0 in reply to robin mu
    TI__Guru** 107810 points

    Hello Robin,

    robin mu said:
    I have read the section "7.4.12 RAW Mode LV / FV Controls" , but i cann't understand, can you give me a suggestion to set FV_MIN_TIME?

    To prevent false detection of FrameValid, FV must be asserted for a minimum number of clocks prior to first video line to be considered valid. The minimum FrameValid time is programmable in the FV_MIN_TIME register 0xBC. Because the measurement is in FPD-Link III clocks, the minimum FrameValid setup to LineValid timing at the Serializer will vary based on the RAW input operating mode.
    A minimum FV to LV timing is required when processing RAW video frames at the serializer input. If the FV to LV minimum setup is not met (by default), the first video line is discarded. Optionally, a register control (PORT_CONFIG: DISCARD_1ST_ON_ERR) forwards the first video line missing some number of pixels at the start of the line.
    The absolute minimum is the lowest amount the device can do, so if FV_MIN_TIME was zero you would see FV high for the absolute min number of FPD3 PCLKs prior to LV.  So what you want to do is check the datasheet of the image sensor and look for a spec about how long this takes for the sensor and set FV_MIN_TIME so that the result of the equation is as large as possible while being less than the value given in the sensor datasheet. 

    Example:
    If Sensor FV_MIN_TIME = 128, and the used Mode is RAW10:
    The required FV to LV delay = Absolute Min + (FV_MIN_TIME x Conversion factor)
    = 5 + (128 x 2) = 261

    The FV_MIN_TIME is programmed in register 0xBC. For this example, FV_MIN_TIME=128 means we have to program in reg 0xBC = 0x80.

    If reg 0xBC = 0x01, this means the required FV to LV delay (RAW10) is = Absolute Min + (FV_MIN_TIME x Conversion factor)
    = 5 + (1x2) = 7

    If reg 0xBC = 0x00, this means the required FV to LV delay (RAW10) is = Absolute Min + (FV_MIN_TIME x Conversion factor)
    = 5 + (0x2) = 5
    Which means, FV must be asserted for a minimum number of clocks = 5, prior to first video line to be considered as valid.

    robin mu said:
    and if the data type is YUV422 10BIT coming from UB933, Can UB962 change it to YUV422 8BIT?

    No, the DES cannot change the data type. This will be forwarded as it was received.

    Additionally, can you provide register dumps from the SER and the DES during the problem case.

  • 0 in reply to Hamzeh Jaradat
    Prodigy 30 points

    Hi Hamzeh,

    dump register as belows:

    11-03 22:44:00.294 0 0 W UB962 reg[0x0]: 0x60
    11-03 22:44:00.294 0 0 W UB962 reg[0x1]: 0x0
    11-03 22:44:00.295 0 0 W UB962 reg[0x2]: 0x1e
    11-03 22:44:00.295 0 0 W UB962 reg[0x3]: 0x40
    11-03 22:44:00.296 0 0 W UB962 reg[0x4]: 0xd0
    11-03 22:44:00.296 0 0 W UB962 reg[0x5]: 0x1
    11-03 22:44:00.296 0 0 W UB962 reg[0x6]: 0x0
    11-03 22:44:00.297 0 0 W UB962 reg[0x7]: 0xfe
    11-03 22:44:00.297 0 0 W UB962 reg[0x8]: 0x1c
    11-03 22:44:00.298 0 0 W UB962 reg[0x9]: 0x10
    11-03 22:44:00.299 0 0 W UB962 reg[0xa]: 0x7a
    11-03 22:44:00.299 0 0 W UB962 reg[0xb]: 0x7a
    11-03 22:44:00.299 0 0 W UB962 reg[0xc]: 0xf
    11-03 22:44:00.300 0 0 W UB962 reg[0xd]: 0xb9
    11-03 22:44:00.301 0 0 W UB962 reg[0xe]: 0x0
    11-03 22:44:00.301 0 0 W UB962 reg[0xf]: 0xff
    11-03 22:44:00.301 0 0 W UB962 reg[0x10]: 0x91
    11-03 22:44:00.302 0 0 W UB962 reg[0x11]: 0x0
    11-03 22:44:00.306 0 0 W UB962 reg[0x12]: 0x0
    11-03 22:44:00.308 0 0 W UB962 reg[0x13]: 0x0
    11-03 22:44:00.309 0 0 W UB962 reg[0x14]: 0x0
    11-03 22:44:00.309 0 0 W UB962 reg[0x15]: 0x0
    11-03 22:44:00.310 0 0 W UB962 reg[0x16]: 0x0
    11-03 22:44:00.310 0 0 W UB962 reg[0x17]: 0x0
    11-03 22:44:00.311 0 0 W UB962 reg[0x18]: 0x1
    11-03 22:44:00.311 0 0 W UB962 reg[0x19]: 0xd
    11-03 22:44:00.313 0 0 W UB962 reg[0x1a]: 0x4
    11-03 22:44:00.313 0 0 W UB962 reg[0x1b]: 0x75
    11-03 22:44:00.315 0 0 W UB962 reg[0x1c]: 0x2e
    11-03 22:44:00.315 0 0 W UB962 reg[0x1d]: 0x0
    11-03 22:44:00.316 0 0 W UB962 reg[0x1e]: 0x4
    11-03 22:44:00.316 0 0 W UB962 reg[0x1f]: 0x2
    11-03 22:44:00.316 0 0 W UB962 reg[0x20]: 0x0
    11-03 22:44:00.317 0 0 W UB962 reg[0x21]: 0x3
    11-03 22:44:00.318 0 0 W UB962 reg[0x22]: 0x0
    11-03 22:44:00.318 0 0 W UB962 reg[0x23]: 0x0
    11-03 22:44:00.318 0 0 W UB962 reg[0x24]: 0x0
    11-03 22:44:00.319 0 0 W UB962 reg[0x25]: 0x0
    11-03 22:44:00.319 0 0 W UB962 reg[0x26]: 0x0
    11-03 22:44:00.319 0 0 W UB962 reg[0x27]: 0x0
    11-03 22:44:00.321 0 0 W UB962 reg[0x28]: 0x0
    11-03 22:44:00.322 0 0 W UB962 reg[0x29]: 0x0
    11-03 22:44:00.322 0 0 W UB962 reg[0x2a]: 0x0
    11-03 22:44:00.322 0 0 W UB962 reg[0x2b]: 0x0
    11-03 22:44:00.323 0 0 W UB962 reg[0x2c]: 0x0
    11-03 22:44:00.324 0 0 W UB962 reg[0x2d]: 0x0
    11-03 22:44:00.324 0 0 W UB962 reg[0x2e]: 0x0
    11-03 22:44:00.325 0 0 W UB962 reg[0x2f]: 0x0
    11-03 22:44:00.326 0 0 W UB962 reg[0x30]: 0x0
    11-03 22:44:00.326 0 0 W UB962 reg[0x31]: 0x0
    11-03 22:44:00.326 0 0 W UB962 reg[0x32]: 0x1
    11-03 22:44:00.327 0 0 W UB962 reg[0x33]: 0x1
    11-03 22:44:00.328 0 0 W UB962 reg[0x34]: 0x0
    11-03 22:44:00.328 0 0 W UB962 reg[0x35]: 0x1
    11-03 22:44:00.330 0 0 W UB962 reg[0x36]: 0x0
    11-03 22:44:00.330 0 0 W UB962 reg[0x37]: 0x0
    11-03 22:44:00.331 0 0 W UB962 reg[0x38]: 0x0
    11-03 22:44:00.331 0 0 W UB962 reg[0x39]: 0x0
    11-03 22:44:00.332 0 0 W UB962 reg[0x3a]: 0x0
    11-03 22:44:00.332 0 0 W UB962 reg[0x3b]: 0x0
    11-03 22:44:00.332 0 0 W UB962 reg[0x3c]: 0x0
    11-03 22:44:00.333 0 0 W UB962 reg[0x3d]: 0x0
    11-03 22:44:00.333 0 0 W UB962 reg[0x3e]: 0x0
    11-03 22:44:00.334 0 0 W UB962 reg[0x3f]: 0x0
    11-03 22:44:00.334 0 0 W UB962 reg[0x40]: 0x0
    11-03 22:44:00.334 0 0 W UB962 reg[0x41]: 0xa9
    11-03 22:44:00.334 0 0 W UB962 reg[0x42]: 0x71
    11-03 22:44:00.335 0 0 W UB962 reg[0x43]: 0x1
    11-03 22:44:00.335 0 0 W UB962 reg[0x44]: 0x0
    11-03 22:44:00.336 0 0 W UB962 reg[0x45]: 0x0
    11-03 22:44:00.336 0 0 W UB962 reg[0x46]: 0x20
    11-03 22:44:00.336 0 0 W UB962 reg[0x47]: 0x0
    11-03 22:44:00.336 0 0 W UB962 reg[0x48]: 0x0
    11-03 22:44:00.337 0 0 W UB962 reg[0x49]: 0x0
    11-03 22:44:00.337 0 0 W UB962 reg[0x4a]: 0x0
    11-03 22:44:00.337 0 0 W UB962 reg[0x4b]: 0x12
    11-03 22:44:00.338 0 0 W UB962 reg[0x4c]: 0x1
    11-03 22:44:00.338 0 0 W UB962 reg[0x4d]: 0x3
    11-03 22:44:00.338 0 0 W UB962 reg[0x4e]: 0x4
    11-03 22:44:00.338 0 0 W UB962 reg[0x4f]: 0x2a
    11-03 22:44:00.338 0 0 W UB962 reg[0x50]: 0x0
    11-03 22:44:00.339 0 0 W UB962 reg[0x51]: 0x0
    11-03 22:44:00.339 0 0 W UB962 reg[0x52]: 0x0
    11-03 22:44:00.339 0 0 W UB962 reg[0x53]: 0x0
    11-03 22:44:00.339 0 0 W UB962 reg[0x54]: 0x0
    11-03 22:44:00.339 0 0 W UB962 reg[0x55]: 0x0
    11-03 22:44:00.340 0 0 W UB962 reg[0x56]: 0x0
    11-03 22:44:00.340 0 0 W UB962 reg[0x57]: 0x0
    11-03 22:44:00.340 0 0 W UB962 reg[0x58]: 0x58
    11-03 22:44:00.340 0 0 W UB962 reg[0x59]: 0x0
    11-03 22:44:00.341 0 0 W UB962 reg[0x5a]: 0x0
    11-03 22:44:00.341 0 0 W UB962 reg[0x5b]: 0xba
    11-03 22:44:00.341 0 0 W UB962 reg[0x5c]: 0xba
    11-03 22:44:00.341 0 0 W UB962 reg[0x5d]: 0x0
    11-03 22:44:00.342 0 0 W UB962 reg[0x5e]: 0x0
    11-03 22:44:00.342 0 0 W UB962 reg[0x5f]: 0x0
    11-03 22:44:00.342 0 0 W UB962 reg[0x60]: 0x0
    11-03 22:44:00.342 0 0 W UB962 reg[0x61]: 0x0
    11-03 22:44:00.342 0 0 W UB962 reg[0x62]: 0x0
    11-03 22:44:00.343 0 0 W UB962 reg[0x63]: 0x0
    11-03 22:44:00.343 0 0 W UB962 reg[0x64]: 0x0
    11-03 22:44:00.343 0 0 W UB962 reg[0x65]: 0x0
    11-03 22:44:00.343 0 0 W UB962 reg[0x66]: 0x0
    11-03 22:44:00.343 0 0 W UB962 reg[0x67]: 0x0
    11-03 22:44:00.344 0 0 W UB962 reg[0x68]: 0x0
    11-03 22:44:00.345 0 0 W UB962 reg[0x69]: 0x0
    11-03 22:44:00.345 0 0 W UB962 reg[0x6a]: 0x0
    11-03 22:44:00.345 0 0 W UB962 reg[0x6b]: 0x0
    11-03 22:44:00.346 0 0 W UB962 reg[0x6c]: 0x0
    11-03 22:44:00.346 0 0 W UB962 reg[0x6d]: 0x7f
    11-03 22:44:00.346 0 0 W UB962 reg[0x6e]: 0xaa
    11-03 22:44:00.346 0 0 W UB962 reg[0x6f]: 0x88
    11-03 22:44:00.346 0 0 W UB962 reg[0x70]: 0x1f
    11-03 22:44:00.347 0 0 W UB962 reg[0x71]: 0x2c
    11-03 22:44:00.347 0 0 W UB962 reg[0x72]: 0xe4
    11-03 22:44:00.347 0 0 W UB962 reg[0x73]: 0x2
    11-03 22:44:00.347 0 0 W UB962 reg[0x74]: 0xff
    11-03 22:44:00.347 0 0 W UB962 reg[0x75]: 0xa
    11-03 22:44:00.348 0 0 W UB962 reg[0x76]: 0x0
    11-03 22:44:00.348 0 0 W UB962 reg[0x77]: 0xc5
    11-03 22:44:00.348 0 0 W UB962 reg[0x78]: 0x0
    11-03 22:44:00.348 0 0 W UB962 reg[0x79]: 0x1
    11-03 22:44:00.348 0 0 W UB962 reg[0x7a]: 0x0
    11-03 22:44:00.349 0 0 W UB962 reg[0x7b]: 0x0
    11-03 22:44:00.350 0 0 W UB962 reg[0x7c]: 0x20
    11-03 22:44:00.350 0 0 W UB962 reg[0x7d]: 0x0
    11-03 22:44:00.350 0 0 W UB962 reg[0x7e]: 0x0
    11-03 22:44:00.350 0 0 W UB962 reg[0x7f]: 0x0
    11-03 22:44:00.351 0 0 W UB962 reg[0x80]: 0x0
    11-03 22:44:00.351 0 0 W UB962 reg[0x81]: 0x0
    11-03 22:44:00.351 0 0 W UB962 reg[0x82]: 0x0
    11-03 22:44:00.351 0 0 W UB962 reg[0x83]: 0x0
    11-03 22:44:00.351 0 0 W UB962 reg[0x84]: 0x0
    11-03 22:44:00.352 0 0 W UB962 reg[0x85]: 0x0
    11-03 22:44:00.352 0 0 W UB962 reg[0x86]: 0x0
    11-03 22:44:00.352 0 0 W UB962 reg[0x87]: 0x0
    11-03 22:44:00.352 0 0 W UB962 reg[0x88]: 0x0
    11-03 22:44:00.352 0 0 W UB962 reg[0x89]: 0x0
    11-03 22:44:00.353 0 0 W UB962 reg[0x8a]: 0x0
    11-03 22:44:00.353 0 0 W UB962 reg[0x8b]: 0x0
    11-03 22:44:00.353 0 0 W UB962 reg[0x8c]: 0x0
    11-03 22:44:00.353 0 0 W UB962 reg[0x8d]: 0x0
    11-03 22:44:00.354 0 0 W UB962 reg[0x8e]: 0x0
    11-03 22:44:00.354 0 0 W UB962 reg[0x8f]: 0x0
    11-03 22:44:00.354 0 0 W UB962 reg[0x90]: 0x0
    11-03 22:44:00.354 0 0 W UB962 reg[0x91]: 0x5b
    11-03 22:44:00.355 0 0 W UB962 reg[0x92]: 0x0
    11-03 22:44:00.356 0 0 W UB962 reg[0x93]: 0x0
    11-03 22:44:00.357 0 0 W UB962 reg[0x94]: 0xff
    11-03 22:44:00.357 0 0 W UB962 reg[0x95]: 0xff
    11-03 22:44:00.357 0 0 W UB962 reg[0x96]: 0x0
    11-03 22:44:00.357 0 0 W UB962 reg[0x97]: 0x0
    11-03 22:44:00.357 0 0 W UB962 reg[0x98]: 0x0
    11-03 22:44:00.358 0 0 W UB962 reg[0x99]: 0x0
    11-03 22:44:00.358 0 0 W UB962 reg[0x9a]: 0x0
    11-03 22:44:00.358 0 0 W UB962 reg[0x9b]: 0x0
    11-03 22:44:00.358 0 0 W UB962 reg[0x9c]: 0x0
    11-03 22:44:00.358 0 0 W UB962 reg[0x9d]: 0x0
    11-03 22:44:00.359 0 0 W UB962 reg[0x9e]: 0x0
    11-03 22:44:00.359 0 0 W UB962 reg[0x9f]: 0x0
    11-03 22:44:00.359 0 0 W UB962 reg[0xa0]: 0x0
    11-03 22:44:00.359 0 0 W UB962 reg[0xa1]: 0x0
    11-03 22:44:00.359 0 0 W UB962 reg[0xa2]: 0x0
    11-03 22:44:00.360 0 0 W UB962 reg[0xa3]: 0x0
    11-03 22:44:00.360 0 0 W UB962 reg[0xa4]: 0x0
    11-03 22:44:00.360 0 0 W UB962 reg[0xa5]: 0x1c
    11-03 22:44:00.360 0 0 W UB962 reg[0xa6]: 0x0
    11-03 22:44:00.360 0 0 W UB962 reg[0xa7]: 0x0
    11-03 22:44:00.361 0 0 W UB962 reg[0xa8]: 0x0
    11-03 22:44:00.361 0 0 W UB962 reg[0xa9]: 0x0
    11-03 22:44:00.361 0 0 W UB962 reg[0xaa]: 0x0
    11-03 22:44:00.361 0 0 W UB962 reg[0xab]: 0x0
    11-03 22:44:00.361 0 0 W UB962 reg[0xac]: 0x0
    11-03 22:44:00.361 0 0 W UB962 reg[0xad]: 0x0
    11-03 22:44:00.362 0 0 W UB962 reg[0xae]: 0x0
    11-03 22:44:00.362 0 0 W UB962 reg[0xaf]: 0x0
    11-03 22:44:00.362 0 0 W UB962 reg[0xb0]: 0x1c
    11-03 22:44:00.362 0 0 W UB962 reg[0xb1]: 0x3a
    11-03 22:44:00.362 0 0 W UB962 reg[0xb2]: 0x15
    11-03 22:44:00.363 0 0 W UB962 reg[0xb3]: 0x8
    11-03 22:44:00.363 0 0 W UB962 reg[0xb4]: 0x25
    11-03 22:44:00.363 0 0 W UB962 reg[0xb5]: 0x0
    11-03 22:44:00.363 0 0 W UB962 reg[0xb6]: 0x18
    11-03 22:44:00.364 0 0 W UB962 reg[0xb7]: 0x0
    11-03 22:44:00.364 0 0 W UB962 reg[0xb8]: 0x8f
    11-03 22:44:00.364 0 0 W UB962 reg[0xb9]: 0x33
    11-03 22:44:00.364 0 0 W UB962 reg[0xba]: 0x83
    11-03 22:44:00.365 0 0 W UB962 reg[0xbb]: 0x74
    11-03 22:44:00.365 0 0 W UB962 reg[0xbc]: 0x80
    11-03 22:44:00.365 0 0 W UB962 reg[0xbd]: 0x0
    11-03 22:44:00.365 0 0 W UB962 reg[0xbe]: 0x0
    11-03 22:44:00.365 0 0 W UB962 reg[0xbf]: 0x0
    11-03 22:44:00.366 0 0 W UB962 reg[0xc0]: 0x0
    11-03 22:44:00.366 0 0 W UB962 reg[0xc1]: 0x0
    11-03 22:44:00.366 0 0 W UB962 reg[0xc2]: 0x0
    11-03 22:44:00.368 0 0 W UB962 reg[0xc3]: 0x0
    11-03 22:44:00.368 0 0 W UB962 reg[0xc4]: 0x0
    11-03 22:44:00.368 0 0 W UB962 reg[0xc5]: 0x0
    11-03 22:44:00.369 0 0 W UB962 reg[0xc6]: 0x0
    11-03 22:44:00.369 0 0 W UB962 reg[0xc7]: 0x0
    11-03 22:44:00.369 0 0 W UB962 reg[0xc8]: 0x0
    11-03 22:44:00.369 0 0 W UB962 reg[0xc9]: 0x0
    11-03 22:44:00.370 0 0 W UB962 reg[0xca]: 0x0
    11-03 22:44:00.370 0 0 W UB962 reg[0xcb]: 0x0
    11-03 22:44:00.370 0 0 W UB962 reg[0xcc]: 0x0
    11-03 22:44:00.370 0 0 W UB962 reg[0xcd]: 0x0
    11-03 22:44:00.370 0 0 W UB962 reg[0xce]: 0x0
    11-03 22:44:00.371 0 0 W UB962 reg[0xcf]: 0x0
    11-03 22:44:00.371 0 0 W UB962 reg[0xd0]: 0x0
    11-03 22:44:00.371 0 0 W UB962 reg[0xd1]: 0x43
    11-03 22:44:00.371 0 0 W UB962 reg[0xd2]: 0x94
    11-03 22:44:00.372 0 0 W UB962 reg[0xd3]: 0x3
    11-03 22:44:00.372 0 0 W UB962 reg[0xd4]: 0x60
    11-03 22:44:00.372 0 0 W UB962 reg[0xd5]: 0xf2
    11-03 22:44:00.372 0 0 W UB962 reg[0xd6]: 0x0
    11-03 22:44:00.373 0 0 W UB962 reg[0xd7]: 0x2
    11-03 22:44:00.373 0 0 W UB962 reg[0xd8]: 0x0
    11-03 22:44:00.373 0 0 W UB962 reg[0xd9]: 0x0
    11-03 22:44:00.373 0 0 W UB962 reg[0xda]: 0x0
    11-03 22:44:00.374 0 0 W UB962 reg[0xdb]: 0x0
    11-03 22:44:00.374 0 0 W UB962 reg[0xdc]: 0x0
    11-03 22:44:00.374 0 0 W UB962 reg[0xdd]: 0x0
    11-03 22:44:00.374 0 0 W UB962 reg[0xde]: 0x0
    11-03 22:44:00.374 0 0 W UB962 reg[0xdf]: 0x0
    11-03 22:44:00.375 0 0 W UB962 reg[0xe0]: 0x0
    11-03 22:44:00.375 0 0 W UB962 reg[0xe1]: 0x0
    11-03 22:44:00.376 0 0 W UB962 reg[0xe2]: 0x0
    11-03 22:44:00.376 0 0 W UB962 reg[0xe3]: 0x0
    11-03 22:44:00.376 0 0 W UB962 reg[0xe4]: 0x0
    11-03 22:44:00.376 0 0 W UB962 reg[0xe5]: 0x0
    11-03 22:44:00.376 0 0 W UB962 reg[0xe6]: 0x0
    11-03 22:44:00.377 0 0 W UB962 reg[0xe7]: 0x0
    11-03 22:44:00.377 0 0 W UB962 reg[0xe8]: 0x0
    11-03 22:44:00.377 0 0 W UB962 reg[0xe9]: 0x0
    11-03 22:44:00.377 0 0 W UB962 reg[0xea]: 0x0
    11-03 22:44:00.378 0 0 W UB962 reg[0xeb]: 0x0
    11-03 22:44:00.378 0 0 W UB962 reg[0xec]: 0x0
    11-03 22:44:00.378 0 0 W UB962 reg[0xed]: 0x0
    11-03 22:44:00.378 0 0 W UB962 reg[0xee]: 0x0
    11-03 22:44:00.378 0 0 W UB962 reg[0xef]: 0x0
    11-03 22:44:00.379 0 0 W UB962 reg[0xf0]: 0x5f
    11-03 22:44:00.379 0 0 W UB962 reg[0xf1]: 0x55
    11-03 22:44:00.379 0 0 W UB962 reg[0xf2]: 0x42
    11-03 22:44:00.379 0 0 W UB962 reg[0xf3]: 0x39
    11-03 22:44:00.380 0 0 W UB962 reg[0xf4]: 0x36
    11-03 22:44:00.380 0 0 W UB962 reg[0xf5]: 0x30
    11-03 22:44:00.380 0 0 W UB962 reg[0xf6]: 0x0
    11-03 22:44:00.380 0 0 W UB962 reg[0xf7]: 0x0
    11-03 22:44:00.381 0 0 W UB962 reg[0xf8]: 0x0
    11-03 22:44:00.381 0 0 W UB962 reg[0xf9]: 0x0
    11-03 22:44:00.381 0 0 W UB962 reg[0xfa]: 0x0
    11-03 22:44:00.381 0 0 W UB962 reg[0xfb]: 0x0
    11-03 22:44:00.382 0 0 W UB962 reg[0xfc]: 0x0
    11-03 22:44:00.382 0 0 W UB962 reg[0xfd]: 0x0
    11-03 22:44:00.382 0 0 W UB962 reg[0xfe]: 0x0
    11-03 22:44:00.382 0 0 W UB962 reg[0xff]: 0x0


    11-03 22:44:00.383 0 0 W UB933 reg[0x0]: 0xb0
    11-03 22:44:00.383 0 0 W UB933 reg[0x1]: 0x30
    11-03 22:44:00.383 0 0 W UB933 reg[0x2]: 0x20
    11-03 22:44:00.384 0 0 W UB933 reg[0x3]: 0xe7
    11-03 22:44:00.384 0 0 W UB933 reg[0x4]: 0x80
    11-03 22:44:00.385 0 0 W UB933 reg[0x5]: 0x35
    11-03 22:44:00.385 0 0 W UB933 reg[0x6]: 0x60
    11-03 22:44:00.385 0 0 W UB933 reg[0x7]: 0x60
    11-03 22:44:00.385 0 0 W UB933 reg[0x8]: 0xbe
    11-03 22:44:00.386 0 0 W UB933 reg[0x9]: 0xbe
    11-03 22:44:00.386 0 0 W UB933 reg[0xa]: 0x0
    11-03 22:44:00.386 0 0 W UB933 reg[0xb]: 0x0
    11-03 22:44:00.387 0 0 W UB933 reg[0xc]: 0x15
    11-03 22:44:00.387 0 0 W UB933 reg[0xd]: 0x15
    11-03 22:44:00.387 0 0 W UB933 reg[0xe]: 0x35
    11-03 22:44:00.387 0 0 W UB933 reg[0xf]: 0x2
    11-03 22:44:00.388 0 0 W UB933 reg[0x10]: 0x17
    11-03 22:44:00.388 0 0 W UB933 reg[0x11]: 0x21
    11-03 22:44:00.388 0 0 W UB933 reg[0x12]: 0x21
    11-03 22:44:00.388 0 0 W UB933 reg[0x13]: 0x0
    11-03 22:44:00.389 0 0 W UB933 reg[0x14]: 0x0
    11-03 22:44:00.389 0 0 W UB933 reg[0x15]: 0x31
    11-03 22:44:00.389 0 0 W UB933 reg[0x16]: 0x80
    11-03 22:44:00.390 0 0 W UB933 reg[0x17]: 0x0
    11-03 22:44:00.390 0 0 W UB933 reg[0x18]: 0x0
    11-03 22:44:00.390 0 0 W UB933 reg[0x19]: 0x0
    11-03 22:44:00.391 0 0 W UB933 reg[0x1a]: 0x0
    11-03 22:44:00.391 0 0 W UB933 reg[0x1b]: 0x0
    11-03 22:44:00.391 0 0 W UB933 reg[0x1c]: 0x0
    11-03 22:44:00.391 0 0 W UB933 reg[0x1d]: 0xa0
    11-03 22:44:00.392 0 0 W UB933 reg[0x1e]: 0x2
    11-03 22:44:00.392 0 0 W UB933 reg[0x1f]: 0x0
    11-03 22:44:00.392 0 0 W UB933 reg[0x20]: 0xe
    11-03 22:44:00.392 0 0 W UB933 reg[0x21]: 0x1c
    11-03 22:44:00.393 0 0 W UB933 reg[0x22]: 0x29
    11-03 22:44:00.393 0 0 W UB933 reg[0x23]: 0x0
    11-03 22:44:00.393 0 0 W UB933 reg[0x24]: 0x0
    11-03 22:44:00.394 0 0 W UB933 reg[0x25]: 0x0
    11-03 22:44:00.394 0 0 W UB933 reg[0x26]: 0x0
    11-03 22:44:00.395 0 0 W UB933 reg[0x27]: 0x0
    11-03 22:44:00.395 0 0 W UB933 reg[0x28]: 0x25
    11-03 22:44:00.395 0 0 W UB933 reg[0x29]: 0x6
    11-03 22:44:00.396 0 0 W UB933 reg[0x2a]: 0x0
    11-03 22:44:00.396 0 0 W UB933 reg[0x2b]: 0x0
    11-03 22:44:00.396 0 0 W UB933 reg[0x2c]: 0x0
    11-03 22:44:00.397 0 0 W UB933 reg[0x2d]: 0x0
    11-03 22:44:00.397 0 0 W UB933 reg[0x2e]: 0x0
    11-03 22:44:00.397 0 0 W UB933 reg[0x2f]: 0x0
    11-03 22:44:00.398 0 0 W UB933 reg[0x30]: 0x0
    11-03 22:44:00.398 0 0 W UB933 reg[0x31]: 0x0
    11-03 22:44:00.398 0 0 W UB933 reg[0x32]: 0x0
    11-03 22:44:00.398 0 0 W UB933 reg[0x33]: 0x80
    11-03 22:44:00.400 0 0 W UB933 reg[0x34]: 0xf8
    11-03 22:44:00.400 0 0 W UB933 reg[0x35]: 0xa

  • 0 in reply to robin mu
    TI__Guru** 107810 points

    Hi Robin,

    Thanks for sharing the reg dumps.

    I have reviewed them. Everything looks good to me. I see absolutely no error reported on the SER or DES.

    However, I can see the received resolution is different than what you shared initially. I see the DES is receiving 1024 x 767. Can you double check your Image sensor configurations?

    Also, can you share with me the other image sensor parameters, such as Frame rate and the expected pixel clock?

    Additionally, I need the Oscillator Clock value on the SER side and on the DES side.