Part Number: TLK10081
Other Parts Discussed in Thread: TLK10232
Tool/software:
Good Day,
i have got problems, to get run the TLK10081 in the 8:1 mode. To symplify the problem, i have tried to operate in the 1:1 mode first, but without success. Below you can find my simplified setup.
No matter, what i have tried in register configurations, i was not able to get run the setup.
Here would be my register configuration:
Just one hint: If i have activated the 8b/10b decoder/encoder, i have activated it on the Lowspeed and Highspeed side.For the deactivation this means the same, Lowside and Highside.
PTAD_PTAD1 = 0; //20ms Reset Phy and TLK10081
Cpu_Delay100US(200); //20ms Delay
//I have also tried Bit Interleave Mode
(void)mdio_write(PHY_ADDR_TLK,CHANNEL_CONTROL_1,0x000C);//Adress 0x01, 1 Channel, Byte Interleave
(void)mdio_write(PHY_ADDR_TLK,HS_SERDES_CONTROL_2,0x6A4E); //Adress 0x03 HS Tx,Rx Quarter Rate,660mVdfpp
(void)mdio_write(PHY_ADDR_TLK,BIT_LM_CONTROL,0x04C8); //Adress 0x18 Disable Lane Marker detection Rx Ls Lane. Normalmode
//I have also tried with FIFO Standard 000
(void)mdio_write(PHY_ADDR_TLK,LS_TXFIFO_CONTROL,0xE2BC); //Adress 0x19 Lowspeed TX FIFO auf Max
//I have also tried with CTC on
(void)mdio_write(PHY_ADDR_TLK,LN_DATA_SRC_CONTROL,0x1000); //Adress 0x1B Disable CTC Rx/Tx
//I have also tried with 8b/10b disabled and Standard FIFO 000, also tried with 8b/10b enabled Standard Setup
(void)mdio_write(PHY_ADDR_TLK,LS_CH_CONTROL_1,0x700C); //Adress 0x1C Disable 8B/10 Encoder/Decoder Lowspeed Rx,Tx, Lowspeed RX FIFO Max
//I have also tried with 8b/10b disabled and Standard FIFO 000
(void)mdio_write(PHY_ADDR_TLK,HS_CH_CONTROL_1,0x770C); //Adress ox1D Disable 8B/10 Encoder/Decoder Highspeed,Marker Search/Replacement off, Rx0/Rx1,Tx FIFO Max
//I have also tried with Lowspeed 8b/10b enabled
//(void)mdio_write(PHY_ADDR_TLK,HS_CH_CONTROL_1,0x0000); //Enable 8B/10 Encoder/Decoder Highspeed,Marker Search/Replacement off
//I have also tried with and without Reset Rx/Tx path
(void)mdio_write(PHY_ADDR_TLK,RESET_CONTROL,0x0008); //Adress 0x0E Reset Tx und Rx Data Path
Below would be the Dump from the Status Register 0x0F,0x13,0x14:
No matter what register change i would do, the Status Dump would allways be the same. The Register reading would be correct, i think, the status change from unlocked to locked, from unsynced to sync and from invalid word decode to valid. The problem would be allways the FIFO Overflow.
Channel Status 1 Register
HS_PLL_Lock: locked
LS_PLL_Lock: locked
LT_RX_STATUS: Receiver Training in Progress
LT_FRAME_LOCK: Training Frame delineation not detected
BIT_LMDONE: Valid Marker Pattern not found
HS_TX0_FIFO_OVERFLOW: CTC No Overflow
HS_TX0_FIFO_UNDERFLOW: CTC No Underflow
HS_DECODE_INVALID: Valid Decode Word
HS_CHANNEL_SYNC: Sync achieved
HS_AGC_LOCKED: locked
HS_AZ_DONE: Auto Zero complete
HS_LOS: No Signal loss
HS_TRAINING_FAIL: Training not failed
HS_TP_STATUS: Alignment not achieved
LS Status 1 Register
LS_RX_FIFO_OVERFLOW: Overflow
LS_RX_FIFO_UNDERFLOW: No Underflow
LS_TX_FIFO_OVERFLOW: Overflow
LS_TX_FIFO_UNDERFLOW: No Underflow
LS_CH_SYNC_STATUS: Synced
LS_RX_LOS_DETECT_LH: No LOS Pattern detected
LS_LOS: No LOS
LS_INVALID_DECODE: Valid decode
LS_RX_LOS_DETECT: No LOS Pattern detected
LS_TP_STATUS: Alignment not achieved
HS Status 1 Register
HS_RX0_FIFO_OVERFLOW: Overflow
HS_RX0_FIFO_UNDERFLOW: No Underflow
HS_RX1_FIFO_OVERFLOW: No Overflow
HS_RX1_FIFO_UNDERFLOW: No Underflow
TX0_LANE_ALIGN: TX0 not aligned
TX1_LANE_ALIGN: TX1 not aligned
RX0_LANE_ALIGN: RX0 not aligned
RX1_LANE_ALIGN: RX1 not aligned
TX2_LANE_ALIGN: TX2 not aligned
TX3_LANE_ALIGN: TX3 not aligned
RX2_LANE_ALIGN: RX2 not aligned
RX3_LANE_ALIGN: RX3 not aligned
