DP83867IR: Queries related to Auto negotiation

Hi Mitesh!

Glad to hear that the customer is considering our DP83867! Yes, Auto-negotiation is supported in all MAC Interfaces, including RGMII, and will work for both Full and Half duplex communication.

1. Yes VDD1P0 is an Analog Supply
2. What is the MDO signal? Are you referring to MDIO? 
3. Are you referring to MDC?
   1. Both the MDC and MDIO signals can be shared between the two PHYs and the FPGA
      1. i.e.
         1. the MDC line goes from the FPGA to both PHYs
         2. the MDIO line goes from the FPGA to both PHYs
   2. The only requirement would be to strap the 867's into different PHY Addresses
4. Just an output clock that can be connected to other components if need. Some applications, like SyncE, require the PHY to output the MDI Transmit clock
   1. by default, CLKOUT outputs the input clock (25MHz), this can be checked to verify if the PHY is alive or not.
      1. would recommend keeping a test point for debugging purposes.
   2. If the customer is not going to use CLKOUT, it can be left floating/no connect. 
5. If the JTAG pins are not being used, they can all be left floating/no connect
6. If configured into INT, the pin will be an output

Regards,

Alvaro

Thanks Alvaro for the input.

Few more queries raised by customer.

I would also appreciate further clarification on the collision detection feature of the DP83867IRRGZ. Could you please guide us on the various methods to enable collision detection with the RGMII interface? One approach I have identified is configuring the LED pins to 0100 for collision indication.

 However, there is a possibility that we may need to repurpose all three LED pins for other functions. If this is the case, could you advise if there are any alternative methods to monitor collision detection?

Regards

Mitesh

Hi Alvaro,

Apart from the previous query, customer has raised few more so pls. help with the response.

      Some more points are there to get clarified.

1. Strapping 867’s PHY address : You mention to strap the PHY address when using common signal from FPGA. Please advice how it can do. When referring to the PHY 867 datasheet the MDC and MDIO Pin type is I,PD and I/O. In that case how to strap the Pins.
2. Hope no plans to EoL DP83867IRRGZ. Please clarify.
3. Collision detection feature of the DP83867IRRGZ. Could you please guide us on the various methods to enable collision detection with the RGMII interface? One approach customer have identified is configuring the LED pins to 0100 for collision indication. However, there is a possibility that they may need to repurpose all three LED pins for other functions. If this is the case, could you advise if there are any alternative methods to monitor collision detection?
4. For Selection LAN transformer they can see that HX5008FNL is the recommended part from TI but unfortunately the part is in NRFD status. Considering the cost, they thought of moving forward with TDK made B78476A8251A003. Please advice whether the part good to integrate with DP83867IRRGZ.
5. They would like to get a recommendation on the tolerance of the LAN transformer turns ratio. In datasheet it is recommended use the part with tolerance 2%. Is there any risk in using the part with 3% and 5%. They can see except Pulse, Wurth and ATEK is providing the parts with 3% and 5% tolerance.
6. In general, is there any topic they need to take care while using DP83867IRRGZ in RGMII interface which is not provided in datasheet.
7.  Customer would like to understand whether they can use DP83867IRRGZ only with 2.5V for IO or two Power supply Configuration is mandatory (2.5V and 1V) for IO

Regards

Mitesh

Hi Mitesh,

1. Please see the Strap Configuration section of the data sheet
2. There are no plans to EOL the DP83867
3. Collision is unused in RGMII, why is the customer looking for this?
4. Please compare the B78476A8251A003's spec to Table 8-1 in the data sheet
   1. Refer to this FAQ for help in reviewing the specs
5. The DP83867 has been validated with transformers with a 2% turn ratio tolerance. We cannot guarantee performance if this spec is not met.
6. The most common issue we see with RGMII is setting the delay for the RX & TX Clock. Please check Figure 6-4 & 6-5 in the data sheet, along FAQ RGMII Timing: Align and Shift Mode 
7. The 1V is mandatory, and a single 2.5V source can supply the voltage for both VDDA2P5 and VDDIO = 2.5V

Regards,

Alvaro

Alvaro,

Customer wants to knwo more on the Collision detection on RGMII since it is a new topic for them, you mean to say that collision detection feature is not relevant for RGMII, If yes could you please let us know what could be the reason.

Regards,

Mitesh

Hi Mitesh,

The COL functionality is intended only for Half-Duplex modes. For Full Duplex, the pin will remain low. In RGMII, this pin is unused and collision is handled by the MAC. Please refer to the RGMII Standard for more information.

4527.RGMIIv1_3.pdf 

Regards,

Alvaro

Hi Alvaro,

Customer has raised few more queries.

1. We were able to see the data for ESD and Emission, Do TI have any performance analysis during Surge and Burst test.
2. Whether the provided JTAG Pins shall be used for Boundary Scan purpose.
3. The power consumption data provided on https://www.ti.com/lit/an/snla237/snla237.pdf?ts=1733809730702&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FDP83867IR is limited to 50%. Could you please let me know what is the reason for the same. Is there a way to get the data for 100% utilization @25C , @85 and @-40C, (Condition: VDDIO : 2.5V, VDDA : 2.5V and Vcore: 1V and VDDIO : 3.3V, VDDA : 2.5V and Vcore: 1V)

Pls. help on above three queries.

Regards,

Mitesh

Hi Mitesh,

Please allow me another day to review and reply.

Regards,

Alvaro

Hi Mitesh,

What ESD Surge and Burst test criteria are you looking for?

Yes, JTAG can be used for boundary scan.

I'm not sure why the Power consumption Appnote (snla241) is using 50% data utilization, I'm afraid this is the data that we have. 

Regards,

Alvaro

Alvaro,

How can we get power consumption with 100% utilization? 

For ESD surge & Burst data what data we have? I understand these are system level implementation but any time tested with EVM or ref. design then also ok for us.

Regards

Mitesh

Hi Mitesh,

May I ask what ESD and surge level are you looking for on IEC testing?

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Regards,

Hillman Lin