TCAN4550-Q1: How can we configure the registers to send the command?

Hi Jonathan,

My customer wonder if there is a way to know that TCAN4550-Q1 has finished data sending， they assume three ways as below, please help to review, thanks in advance!

1. Set the Message RAM Access Failure Interrupt Enable and Message stored to Dedicated Rx Buffer Interrupt Enable

Write 0X1054 Register, 0XA01

Write 0X105C Register, 0X03

Write 0X0800 Register, 0XC8400480

2.Read 0X0824 register bit 9 for Transmission Completed

Write 0X1054 Register, 0XA01

Read 0X0824 Register, bit 9

3. Compare below registers：

Read 0X10C4， then compare bit16~20 and bit8~12

But all of them are failed, need your help to realize it.

Best Regards，

Jack

Hi Jack,

The Transmit Complete Interrupt bit should get set when a message was successfully transmitted.  It looks like they have correctly enabled that bit. 

I don't have any understanding why they think the Message RAM Access Failure Interrupt bit would indicate a transmission complete.  This is a fault bit that should not get set under normal operation.

I would again refer you to the M_CAN User's Manual (Link) and section 3.5 as well as the various bit descriptions for the registers for all of the information available on the TX Handling.

It is not clear that the device is actually transmitting a message, and there could be other configuration issues leading to the message not getting transmitted.  The full register configuration would need to be verified to check for errors.

Generally the TX process is as follows:

- A message is loaded into a TX Buffer element in the MRAM.

- The bit corresponding to the TX Buffer element that was used for the message is set to "1" in the TX Buffer Add Request register (0x10D0).

- The device will then set the corresponding bit in the TX Buffer Request Pending register (0x10CC).

- Once the message has been successfully transmitted, the device will clear the bit in the TX Buffer Request Pending register (0x10CC) and set the corresponding bit in the TX Buffer Add Request Transmission Occurred register (0x10D8).

- The device should then also set the Transmission Occurred Interrupt bit in the Interrupt register (0x1050 and 0x0824).

If the TX Event FIFO is configured, an event element will be added to the next available buffer in the TX Event FIFO.

- If a TX FIFO or Queue is used, the Put and Get indexes will be updated.

I would suggest monitoring the values of 0x10CC and 0x10D8 for direct information on the status of the TX Buffer containing the message they are using.

Regards,

Jonathan

Hi Jonathan,

Jonathan Nerger said:

I don't have any understanding why they think the Message RAM Access Failure Interrupt bit would indicate a transmission complete.  This is a fault bit that should not get set under normal operation.

Thanks for your reply, my customer want to use interrupt to indicate if the CAN data has been send, please help to tell us how to configure these registers, thanks in advance!

1. Set the Message RAM Access Failure Interrupt Enable and Message stored to Dedicated Rx Buffer Interrupt Enable

Write 0X1054 Register, 0XA01

Write 0X105C Register, 0X03

Write 0X0800 Register, 0XC8400480

Best Regards,

Jack

HI Jack,

To generate an interrupt that will indicate a CAN message transmission was complete, you will need to set the following bits to "1".

The Transmission Completed Interrupt Enable bit (bit 9) in the Interrupt Enable register (0x1054).

Note that MCAN has 2 interrupt lines and by default all interrupt bits are assigned to "Line 0" in the Interrupt Line Select Register(0x1058). 

The Enable Interrupt Line 0 should be set (bit 0) in the Interrupt Line Enable register (0x105C) if the interrupts were assigned to Line 0 (default).  If any interrupt bits were assigned to Line 1 then the Enable Interrupt Line 1 should be set as well (bit 1).

Then when a message CAN message has successfully transmitted the Transmit Completed bit (bit 9) in the Interrupt Register (0x1050 and 0x0824) will be set to "1". 

Note that register 0x0824 is just a read-only copy of register 0x1050, so writing a "1" to bit 9 of register 0x1050 is required to clear this bit.  Writing to register 0x0824 has no effect and will not clear this bit.

Regards,

Jonathan