DP83867IS: Issue with DP83867 PHY SGMII Configuration on Custom SMDC Board

Hi,

Judging by the fact that the PHY specific drivers cannot be loaded, it seems that the PHY is not actually being recognized. Can you confirm the following to rule out some possible causes?

Are you able to access the memory registers of the PHY? This can be checked by trying to read registers 0x02/0x03, which form a unique identifier for the PHY and cannot be 0x0000, or 0xFFFF. If you can read these registers, then the memory access should be okay

Is the PHY getting appropriate voltages at the power pins? Note: Probe as close to the PHY pins as possible for these measurements

Best,

Vivaan

Vivado Configuration
Configured the Zynq UltraScale+ MPSoC in Vivado, focusing on the following:Enabled GEM 0 with i/o GT LANE 0 for Ethernet functionality with the SGMII interface.
Verified the PS (Processing System) configuration, ensuring the necessary GT Lane reference frequency all are initialised with refclk0 with input frequency 125mhz.  
Integrated the required peripherals, including GPIO, UART, and DDR4 memory.
Generated the bitstream and exported the hardware design as an XSA file for PetaLinux integration.

 PetaLinux Project Setup
Created a PetaLinux project using the exported hardware description file (XSA) 
Imported the hardware configuration and build the project 

i am working on boot strap with sgmii mode and mpsoc with rx+- and tx+- 

Is common clk required for the mpsoc tx an rx? 

 I would appreciate any suggestions or guidance on troubleshooting this further. If additional information or logs are needed, please let me know, and I will provide them. 

Hi Litesh,

I noticed that the MDIO pull-up resistor is DNP on the schematic, This is probably why there is no register access for this device at the moment, and why the drivers are not loading properly. Adding this PU resistor should help with driver detection and register access

LItesh G said:

While I am able to successfully ping the SMDC board from the PC, I am unable to ping the PC from the SMDC board. The error I receive when trying to ping the PC from the board is: "Destination Host Unreachable. 

Could you share the ping log for this working case?

LItesh G said:

Is common clk required for the mpsoc tx an rx? 

For SGMII, the clock is usually built into the differential signal itself, which is then separated at the receiver, or sometimes an additional pair of signals can be used to make it 6-wire SGMII carrying the common 625MHz frequency. Is this setup using 4 or 6 wire SGMII?

Best,

Vivaan

Hi Vivaan , 

I have set up my wired connection manually 

I am making the eth0 up and assigning the ip and if i ping that ip it is pinging , but what ip i have assigned in my wired settings manually that ip isnt pinging . 

By the way i am using 4-wire SGMII 

Hi Litesh, 

Thank you for the ping log.

First, I wanted to make sure that the drivers are loading properly. Were you able to add the resistor on the MDIO line?

This would also help us get memory access to debug properly. 

Best,

Vivaan

Hi Vivaan 

To address this, I made the following changes:

1. Removed R429: This resistor, which was marked as DNP (Do Not Place) and 0 ohms, was causing an open circuit on the MDIO line.
2. Shorted R431 and R432: These were shorted to ensure proper routing and signal integrity for the MDIO and MDC lines.
3. Used Jumper Wires: I have temporarily routed the MDIO and MDC lines to the Ethernet pins using jumper wires to bypass potential PCB layout issues.

Despite these changes, I am still unable to detect the PHY using MDIO commands. The PHY does not respond to register reads, and the driver is not loading correctly.

Could you please advise on additional steps I can take to debug this issue or confirm

And i have enabled mdio under gem in vivado 2020.1 

And i am not able to see the ethernet only 

Hi Litesh,

LItesh G said:

Removed R429: This resistor, which was marked as DNP (Do Not Place) and 0 ohms, was causing an open circuit on the MDIO line.

I am a little confused by this. The schematic shows that the resistor is not DNP, but placed. Did you remove this resistor? If so, this would disconnect the MDIO line to any devices connected to MPS1_ETH net. 

LItesh G said:

Shorted R431 and R432: These were shorted to ensure proper routing and signal integrity for the MDIO and MDC lines.

This enables devices connected to MPS2_ETH to the CPU. 

Even in this configuration, a pull up resistor on MDIO is still a requirement that has not been met. Resistor R427 must also be placed for meeting this requirement and enabling MDIO communication. 

I would also verify that the PHY address of the PHY you are trying to connect to over MDIO is correct. T

LItesh G said:

And i am not able to see the ethernet only 

This might be due to removing the resistor R429.

Best,

Vivaan

Hi Vivaan , 

So basically we are working on mpsoc2 

can u tell me what to put in system-user.dtsi file i mean the device tree snippet 

Hi Litesh, 

I believe the file you are referring to is native to the SoC. Since the SoC is not a TI part, I am unable to help with its configuration parameters. 

Looking forward to seeing if adding the PU resistor helps with MDIO access to the PHY

Best,

Vivaan