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Original question:

DP83869HM: Setting up Digital Loopback & Confirming Results

DP83867IS: Digital loopback issue

Krishna Kalipurath Radhakrishnan
Prodigy 10 points
Part Number: DP83867IS

Tool/software:

Hello,

I am trying to put the DP83867ISRGZ phy on the VCU118 board in loopback and send and recieve data from the MAC(with an sgmii adapter interface) in my FPGA design, for a throughput analysis exercise. From the software test I am doing, I see that the MAC is not sending or recieving any data. 

The phy digital loopback configuration I did is as follows


Write register 0x00FE with value 0xE720
Write register 0x0 with value 0x0140
Write register 0x0010 with value 0x5028
Write register 0x0016 with value 0x0004
Write register 0x001F with value 0x4000

To sanity check the PHY, I tried some PRBS tests as below

Write register 0x0016 0xF004
Write register 0x0072 0x0201
Read register 0x0071 : Value recieved : 0x8405
Read register 0x0072 : Value recieved : 0x200
Read register 0x01a8 : Value recieved : 0x8f6
Read register  0x01a9 : Value recieved : 0x0

From the documentatin, what I understand is that the PRBS test is recieving some data and does not detect any errors.

I am seeing a link up status in the phy registers too. 

I am wondering then why my MAC is not able to send and recieving any data. 

I have tested with PHY not in loopback and I can send data out. However when I put the phy in digital loopback, I am not able to do that even with the link up status. 

Do you have any clue?

  • 0
    TI__Expert 6385 points

    Hi Krishna,

    Thank you for your explanation. I wanted to align on a few things.

    You mention that the MAC doesn't seem to be sending or receiving data with digital loopback. How are you checking if the MAC is sending data? Are you probing the connections?

    Moreover, I can see that PRBS can account for some packets being received. Is this in the loopback case or the case without loopback? 

    Best,

    Vivaan

  • 0 in reply to Vivaan Jaiswal
    Prodigy 10 points

    Hi Vivaan,

    Thank you for the reply.

    In the FPGA design I have an Gigabit Ethernet controler IP which can be configured to send data to the PHY. The Ethernet controller reads the descriptors that are set up by the software and sends out data using a DMA engine and updates the descriptor after sending.When I set the phy in 'NOT loopback' mode, and run the test I can see that the transmission happens correctly, the ethernet controller updates my descriptors after sending the data out. 

    When I configure the PHY in loopback mode, I could see that the link up status is '1' from phy. However I see that none of my descriptors are updated which indicates that the transmission is not happening. And there is a timeout in my test and I hit that. This points to data not being transmitted.

    Then I tried the PRBS test as described in the PHY user manual, with PHY set in loopback, to see if that works.

    Please see my system set up below.

    Would it be something related to the clock that comes into the SGMII interface from the PHY, when the phy is in loopback? Is there a way to verify that clock is running properly?

    Regards,

    Krishna

  • 0 in reply to Krishna Kalipurath Radhakrishnan
    TI__Expert 6385 points

    Hi Krishna, 

    Thank you for the detailed explanation of your setup.

    Would it be possible for you to verify that the packets are not being sent by probing the TX line going into the PHY?

    It looks like the packets are being recognized by the PHY since we can see them in the PRBS counter registers while in loopback.

    It may be software behavior that is the cause of the descriptors not being updated. Putting the PHY in loopback disconnects the MDI line from the datapath. Perhaps the trigger for updating the descriptors is being missed when enabling loopback mode. 

    Best,

    Vivaan