DP83TG721R-Q1: Is there any recovered clock output that can be used for synchronization with SPE?

Hi Cody,

Do you have a block diagram of what you are trying to do?

The DP83TG721 should be capable of this, as it has the ability to use the recovered MDI clock as the 1588 clock source and can generate waveforms based off that clock source, up to 50MHz. I will to check if timestamps need to be used.

Best regards,

Melissa

Hi Melissa,

Thanks for your response! I am basically trying to see whether it is possible to implement something equivalent to Synchronized Ethernet, or SyncE (https://en.wikipedia.org/wiki/Synchronous_Ethernet) over Single-Pair Ethernet. For "standard" multi-pair Ethernet, the PHY will generally provide the recovered clock as output on a pin, which can be used to drive a PLL, which cleans and stabilizes that clock, so that the same clock can be used to drive an Ethernet PHY normally (in place of a traditional crystal). The idea is to share the same clock on all Ethernet-connected devices, so that clock synchronization can be achieved. Since you were asking for a block diagram, maybe something like this will be clear:

Also see TI's AN-1730 (https://www.ti.com/lit/an/snla100a/snla100a.pdf), where Figures 2 and 3 show the type of thing I'm talking about, where the recovered receive clock is used in the PHY instead of an independent clock generated on the slave by a crystal oscillator. That Application Note is for an older multi-pair Ethernet PHY, but the principles are basically the same.

What you say is exactly what gives me hope. I know that the DP83TG721 must be recovering the clock and using it internally for PTP/1588. However, I don't see where that recovered clock is provided as an output on one of the pins. Or, absent that, I don't see any other way to achieve synchronization of multiple Ethernet-connected devices.

For additional context, here is another document describing the idea of Synchronized Ethernet: https://www.microsemi.com/document-portal/doc_view/126475-the-basics-of-synchronized-ethernet-synce. Specifically, please see Figure 3, which shows the idea of passing the recovered clock in order to synchronize all Ethernet-connected devices, as opposed to the more traditional setup in Figure 2, where only the adjacent two nodes are synchronized.

I hope this helps to explain what I am asking about. I have not seen any discussion either in the TI forums or elsewhere online about achieving SyncE with SPE, but it seems like the concept should be the same as for standard multi-pair Ethernet and thus it should be possible to do so. My main question is the practical one: how? SPE PHYs don't seem to provide the recovered clock output like the multi-pair Ethernet PHYs such as the DP83867/DP83869 does via the CLK_OUT pin.

Thanks,
Cody

Hi Cody,

It seems you will have to use timestamps to calcualte the intitial delay. However, once this delay is accounted for, the generated waveforms from the PHY will remain synced as long as the PHYs are correctly configured.

We have some additional resources on how to do this with the DP83TG721, but they require NDA. If you would like to access these resources, I recommend reaching out to your local TI Field Representative.

Best regards,

Melissa

Melissa,

Thanks again. This does sound interesting. I still don't know how I get the waveforms from the PHY, though.

I already have a signed NDA on-file with TI as part of receiving information about another product. Can you verify that on my account and email me the information? Or do I still need to contact someone else? How would I go about doing that?

Thanks,
Cody

Hello,

Thank you for your query. We are having limited support due to holiday season. Please expect a response by Tuesday, January 1 at latest.

Sincerely,

Gerome