DP83869HM: BDSL file

Hi Hanno,

Here is the latest version of BSDL file for DP83869. Unfortunately this model has not been validated completely, and should only be used for evaluation / preliminary testing.

dp83869_bsr_48_untested.bsdl

Please let me know if you have any challenges while using this file.

Thank you,

Evan

Evan, while I appreciate the effort, we haven't seen the desired outcome yet. We still require a solution.

Hi Tomasz,

Could you please share more context on the testing performed with this file?

Feedback would be valuable so I can relay with design team.

Thank you,

Evan

It looks like the length of the instruction registers is not correct, 9 instead of 8bits. Also the Capture Values seems to be incorrect.

Hi Tomasz,

Thanks for confirming. I am relaying this feedback to design, will share updates when able.

Thank you,

Evan

Hi Tomasz,

Following up here, discussions with design team are still in progress to validate this BSDL file.

I am still looking into this, will share updates as soon as possible.

Thank you,

Evan

Hi Tomasz,

I have an update from our design team:

I looked at the E2E thread and see that all posts mention the instruction width being 9-bits in the BSDL file but when I look at the BSDL files in the post all of them have instruction width defined as 8-bits and all the instructions are also 8-bits.

Has customer tried bypass mode on 869 and confirm the tdi is routed to tdo?

Thank you,
Evan

To load the bypass, I first need to load the "Bypass" instruction. But I can't do that because I have to shift 9 bits, but the BSDL file says it's only 8 bits. Therefore, with this statement, I unfortunately don't know what to do.

The question is precisely why I have to shift 9 bits?

Yes, we are shifting a defined pattern (8 bits, our test byte (0x52H)) through the scan chain. And we see that exactly after 9 bits, this pattern comes out of the chain again. Therefore, we see that we are loading something into the chain (TDI) and something is coming out again (TDO). And that while shifting the instruction.

Evan, Could you send me the ofiicial BDSL file, so we have the same basis?

Is it also possible to get a file from here:

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1199023/dp83869hm-bsdl-file-request

Hi Tomasz,

I am confirming this with design, will share feedback by Wednesday 3/5.

Thank you,

Evan

Hi Tomasz,

This is the same BSDL file.

Could you please share capture showing JTAG signal and clock toggle in your case? We are validating equivalent setup to observe 9bit coming out of the chain.

Thank you,

Evan

Dear Evan, We've acquired an additional DP83869EVM for testing purposes. We'll be sharing captured signal data with you shortly. This is to supplement our analysis,in case of any deficiency in our current design.

Hi Tomasz,

Thank you for the update, I will review signal data with design when shared.

We are from goepel electronic and support Thomasz Krupski. We have the DP83869EVM eval board to analyse the boundary scan test. I see in this thread the same behavior. We connected the JTAG signals TCK(#21), TMS(#23), TDI(#24) and TDO(#22).

We set the strapping pins OPMODE(2-0) to high. we set the jumper J19, J11 and J10. Repower the eval board

We send always a testbyte. At the first shift we see that testbyte was shifted with a ofset of 1 bit. So the bypass register should be active.

But if we try to shift an instruction the instruction lenght show us a leght of 9 bits. Also the capture values from the BSDL model dp83869_bsr_48_untested.bsdl

attribute INSTRUCTION_CAPTURE of dp83869_bsr : entity is "11011101";

We can not see the defined instruction capture value? Why?

You see our debug window. On column TDO you see what we send to the DP83869 and on TDI you see what we resceive vom the device.

So on the first shift our testbyte we resceive after offset of 1 bit. Its fine.

But after try to shift a instruction we found see our testbyte not after 8 bits but after 9 bits. So for our understanding the device DP83869 is not in the correct JTAG boundary scan mode. Some oder conditions lost? Or the BSDL model is wrong.

We need more detail inputs to solfe this issue for the boundary scan mode.

Please help.

Hi Jan,

Thank you for sharing the detailed procedure and result. I am reviewing with design team, will share feedback ASAP.

Best regards,
Evan