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TMDS181: SI eye patten test failed

Rannie Zhou
Expert 4160 points
Part Number: TMDS181

Tool/software:

Hi team,

Below are customer's eye pattern test results, which work well with refresh 30 but failed with refresh 60. Do you have any insights on how to optimize it?

refresh 30:

refresh 60:

Sch:6404.HDMI Re-timer 线路12.24.pdf

Note: In sch, customer used skip wire to connect the SCL_CTL/SDA_CTL to host and configure through I2C. I2C_EN is also enabled after checking.

Support need:

  1. Could you please help to give some adjustment suggestion to help customer complete the eye pattern test? such as, register modification... I have asked customer try to set to adaptive EQ mode and will post the results to you later.
  2. It's found that there is a drop on the waveform. Could you please also help to check the reason and how to fix it?
  3. BTW, do we have any documents on how to configure the re-timer based on the eye pattern test?

Thanks!

BRs,

Rannie

  • 0
    TI__Guru**** 177011 points

    Rannie

    Can you please share the actual compliance report and the full TMDS181 I2C register dump between the refresh 30 and refresh 60?

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    TI__Expert 4160 points

    Hi David,

    Please see the attachment for customer's test and register dump summary:TMDS181 test and register dump.pptx

    refresh30 fail: 4096x2160 --refresh 30.pdf

    refresh30 pass but no margin:7-03K 0X0b 0x18 0x0d 0x01.pdf

    refresh 30 pass but pass but Date VL less than 2.6V :7_03K 0X0b 0x18 0x0d 0x01 0x0c 0x40.pdf

    BRs,

    Rannie

  • 0 in reply to Rannie Zhou
    TI__Expert 4160 points

    Hi David,

    Thanks a lot for your reply and support!

    1. Customer would like to operate at below refresh rate and resolution. Their configuration is shown as below:

    4096x2160 --refresh 60 & 4096x2160 --refresh 30  0x0B-0x18

    720x480 --refresh 60 0x0B-0x02

    Could you please help to check whether it make sense?

    2. Can we support a template code or driver in Linux kurnel6.1 system for this configuration?

    3. Another support need is can we support the register configuration with a good VSwing and VL?

    BRs,

    Rannie

  • 0 in reply to Rannie Zhou
    TI__Guru**** 177011 points

    Rannie

    For 4k@60Hz, 0x0B -> 0x1B, this will set TX termination to 75 to 150ohm, and write TMDS_CLK_RATIO_STATUS to a 1. 

    For 4k@30Hz, 0x0B -> 0x08, this will set TX termination to 150-300ohm, and write TMDS_CLK_RATIO_STATUS to a 0.

    For 720x480@60Hz, 0x0B -> 0x00, this will set TX termination to open termination, and write TMDS_CLK_RATIO_STATUS to a 0.

    On the TMDS_CLK_RATIO_STATUS bit and TX termination, they have to set the termination to 75-150ohm and TMDS_CLK_RATIO_STATUS to a 1 per the HDMI2.0 spec. If they set the TMDS_CLK_RATIO_STATUS bit to a 0, then the TMDS CLOCK output will be divide by 4 instead divide by 1, so the clock frequency will be wrong and they will have functional issue.

    Unfortunately we do not have a template code or driver for Linux since these are just I2C writes. They can also switch to pin strap mode and let TMDS181 automatically configures itself base on the DDC snooping and line data rate. 

    Since each design is different, they will have to tune VSADJ and the register configuration to find a good value that can meet both the VSWING and VL requirement.

    Thanks

    David