Tool/software:
Hi Team,
This question is a continuation of the following thread:
The following response was given in this thread:
When there are maximum IDLE errors, it might be the FIFO or the clock frequency different between the processor and the PHY. One thing I would check is the average clock frequency between the processor clock signal and PHY's clock signal.
I have a question about this.
The customer is using SGMII 4-wire embedded clock.
The clock that causes the idle error is SIP/SIN, SOP/SON or XI/XO?
Best Regards,
