TLK10232: Design and debug questions

Hi Joerg,

I'm still looking into this and will get back to you with feedback by early next week.

Best,

Lucas

Hi Joerg,

My apologies for the delay.

Regarding REFCLK:

• REFCLK input should have 100-ohm differential impedance. EVM schematics is the best design to reference.
• Here are several TI oscillators which I believe should meet specifications. link

Here is the bringup procedures document.

5001.tlk10232_BringupProcedures_v2.pdf

Regarding XAUI bridge:

I see in CHANNEL_STATUS_1 register that there is FIFO underflow. I recommend reading Appendix A: Provisionable XAUI Clock Tolerance Compensation in the datasheet and adjusting FIFO depth and watermark settings.

Best,

Lucas

Hi Lucas,

Thanks for your feedback and the bringup document.

REFCLK:

Currently we have mounted an XO on our boards which have a rise/fall time specification (20% to 80%) of 300ps (typ) and 500ps (max.). Could you say if this could somehow relate to the issues we see resp. which kind of consequences of not meeting the rise/fall times one have to expect?

Meanhwile I'm about to look for and order XOs which safely meet the spec (thanks for the link too). Anyway I want to understand if the issue we see can relate to the XO or not.

XAUI bridge:

We did already "play" around with the FIFO settings but had no success. In theory (actual measuremnts still need to be taken) the clock deviation should be less than 10ppm in our case and we were testing with rather small packets of 512B only, so we wonder why the FIFO reports underrun at all. Hence, we try to think of other reasons for the issue (see also the REFCLK discussion) and how to check them. If you have anthing in mind please let us know.

Due to the fact that nothing is connected to the KR ports (yet), both of the HS sides report LOS. Is this something which can be ignored in our loop constellation?

Thank you for further feedback & support.

BR
Joerg

Hi Joerg,

I'm still looking into this and will get back you with feedback by the end of this week.

Best,

Lucas

Hi Joerg,

I believe it's possible that your XO rise/fall time could be responsible for the underflow issue.

Yes, you can ignore statuses related to the HS side because it is unused.

Can you confirm the correct refclk is selected in register 0x1E.0001?

Can you try disabling auto-negotiation in register 0x07.0000?

Best,

Lucas

Hi Lucas,

Thank you for your feedback.

Refclk selection is correct (we have connected REFCLK0 on our boards): device 0x1E register 0x0001 value: 0x0b24 

Disabling autoneg had no influence. But as we face other issues in terms of stability and functionality (only one direction appears to work) we are going to focus on the LS switch configuration again for now. We use the following settings for this:

0x7.0000 AN_CONTROL Default 0x3000: clear AN_ENABLE: 0x2000
0x1E.000B LOOPBACK_TP_CONTROL Default 0x0D10: Enable shallow local loopback: 0x0D11
0x1E.001A DSR_CONTROL_2 Default 0x4C20: Select alternate channel LS output, any data: 0xAC20

In this setup we are still facing our FCS errors (at a low rate) and channel status reports 0x748F (or sometimes 0x7C8F). For our switch constellation everything should be okay according to this, shouldn't it?

Do you see any chance on your side to reconstruct our setup in practice?

I'm still about to get me some sample XOs which meet the TLK specs. Hopefully they will be with us shortly and improves behavior.

BR
Joerg

Hi Joerg,

Thank you for clarifying refclk selection and trying disabling AN.

I'm a bit confused, are you using shallow local loopback in combination with "select alternate channel LS input" (0x1e.001a=0xac20)? Have you seen this configuration perform differently from shallow local loopback in combination with "select alternate channel HS input" (0x1e.001a=0xec20)? Or "select alternate channel LS input" (0x1e.001a=0xac20) without shallow local loopback?

Best,

Lucas

Hi Lucas,

Thanks for coming back. Here is a short summary of our current test status:

* select alternate channel HS input + shallow loopback: only one direction is passing traffic (w/ FCS errors)

* select alternate channel LS input: traffic passing in both directions (w/ FCS errors in both directions)

* select alternate channel LS input + shallow loopback: same as the setting before (loop setting was added in order to get other blocks into a more stable/predictable state due to the unconnected HS side)

Still our hope is on XOs better meeting the specs for rise/fall time (waiting for samples).

Do you have the possibilty to somehow set up our case and test yourself?

Thanks for your support.

BR
Joerg

Hi Joerg,

Thank you for the clarification on your testing status.

Currently I do not have the resources to try reproducing the issue in a bench setup.

Best,

Lucas

Hi Lucas,

Thanks for your reply.

Today I have another update:

We have replaced the XO with SiT9366AI-1E2-33N156.250000 from SiTime and re-test the behavior. Unfortunately the FCS errors are still there and haven't changed in frequency.

So, while waiting for further XO samples (of LMK61E0-156M25SIAT) I ask you to think again of other things to check.

Thanks for your support.

BR
Joerg

Hi Joerg,

I'm still looking into this and will get back to you shortly.

Best,

Lucas

Hi Lucas´,

Meanwhile the samples of LMK61E0-156M25SIAT are with us. Unfortunately initial testing with these showed same behaviour. 

Can somebody please sketch the proper connection of LMK61E0-156M25SIAT to the TLK10232 refclock interface (incl. termination resistor values etc.)?
This should help to exclude any mistakes on our side.

Thank you.

BR
Joerg

Hi Joerg,

TLK10232 expects LVDS or LVPECL reference clock, so I believe either of the following designs can be used.

Best,

Lucas

Thanks, Lucas.

Just for a final confirmation: There is no need for a DC termination at the Refclk inputs of TLK10232 when driven by LVPECL? Or is there internal termination? The pin list mentiones DVDD as reference but Refclk swing is up to 2000mVpp, so I wonder how the internal circuit looks like.

Maybe you can find our more about this...

BR
Joerg

Hi Joerg,

Judging from LMK61xx datasheet diagrams and TLK10232EVM schematics, I believe termination should be connected as shown in Figure 13 for LVPECL.

Best,

Lucas

Hi Lucas,

My question was about DC termination at the inputs of TLK10232 (i.e. behind the coupling capacitors). Could you please confirm that TLK includes all needed components and there is no need for external termination?
Acc. to our measurements there appears to ba a DC offset of approx. 0.8V on the input pins.

Thank you...

BR
Joerg

Hi Joerg,

That's correct, there is no need for external termination between TLK and AC coupling.

I'm a bit confused that you see a DC offset of 0.8V at TLK input pins? Shouldn't the AC coupling caps block any DC offset from reaching the input pins?

Best,

Lucas

Hi Lucas,

The DC offset results from the internal circuit in the TLK10232. Maybe you can consult the designer of the chip or any detailled documentation to confirm/explain this. It should also be measurable on the EVB w/o much effort.

Knowing the internal circuit would help to better understand the topic.

Thank you...

BR
Joerg

Hi Joerg,

I understand, thank you for the clarification. Unfortunately this is a legacy device and the original designers are no longer at TI. My recommendation still stands, there is no need for external termination between the TLK and AC coupling capacitors. This is supported by the TLK10232EVM board schematics, which do not include external termination.

Best,

Lucas

Thanks, Lucas.

Let's "park" the XO topic for a moment.

We will start to bring up the KR side of the switches too (based on the available docs we have). Let's see how this progresses and if the FCS issue on the XAUI side is present in this configuration too or other things show up.

I'll keep you posted.

BR
Joerg

Hi Joerg,

Sounds good, thank you for the update.

Best,

Lucas