DP83867IS: Legacy Scrambler Mode in 1G PCS Master Mode

Hi Kato,

There is a similar E2E thread in-progress that covers most of these questions. Is this related to the linked thread?

e. Are you noticing legacy scrambling mode being enabled by the PHY when connecting with a link partner? This should not be the case, however you can try setting 0x50 bit 1 to '0' as described in the linked thread.

f. I'm not aware of any competitor part numbers that operate in legacy scrambler mode. It seems that this mode was intended to be used for testing with a specific PHY. I'm unsure which PHY that is, however legacy mode should not be used in normal operation.

g. I would need to look into this further. My recommendation is to only operate the PHY in normal encoding mode as this is the intended use.

Best,

Shane

Hi Shane-san,

Thank you for your quick response.

Yes, my post is an issue related to the linked thread.
There has been no update and our customer is very frustrated, so could you please let us know the details of legacy scrambler mode within a week?
I found that the newer DP83869HM has the function to disable the automatic selection of legacy scrambler mode, which is LEGACY_CODING_TXMODE_EN register. So, please confirm if DP83867IS has the same function as hidden register and consider answering my questions a. to g. above again.

It would be very helpful if you could give me some advice quickly.

Best regards,
Kato

Hi Shane-san,

I'm sorry I didn't explain it enough.
I am a colleague working with Takahashi-san and am looking forward to hearing the detailed information from you.

Best regards,
Kato

Hi Kato,

I see from the linked E2E thread that the PHY is in normal mode when communication is working, and reverts to legacy mode when communication is poor. Is there a specific test you're running when you see these communication issues and the PHY switching into legacy mode? 

Can you share a schematic of the DP83867 implementation as a pdf? I'd like to see whether you have this device configured correctly. If you'd like to share this privately, you can accept my friendship request and use the direct message feature on E2E. This will create a separate space that is only viewable by you and I:

Its possible there is an implementation issue that is causing your problem unrelated to the scrambler mode. By reviewing the schematic and layout we can rule that out before narrowing in on legacy mode vs normal mode. In the meantime, I'll work with Vivaan from the linked E2E post to get more info on legacy mode.

Best,

Shane

Hi Shane-san,

Thank you for your support.

I just accepted your friendship request. So, I will organize the information and share details with you via private message within today.

Best regards,
Kato

Sounds good, I will await your private message.

Best,

Shane

Hi Shane-san,

I just shared the detailed information with you via a private message. Please confirm them.

Best regards,
Kato

Hi Kato-san,

I see the schematic, and the detailed information you provided. I will take a look today and follow up in our direct message. 

Best,

Shane

Hi Shane-san,

Thank you for reviewing the schematic and board layout.

I just added the information with you via a private message.

Best regards,
Kato

Hi Kato-san,

Thank you for the information. I'm looking into legacy mode internally, so in the meantime lets try a few things that may help:

1. Try setting register offset 0x14h bit 2 to '0'. I realize this is in the DP83869 datasheet, however sometimes these parts share registers that aren't always documented. I'd like to see whether this stops legacy mode from being enabled on the PHY:

2. Can you try lowering the resistance between the oscillator/clock buffer output and the PHY XI pin? the 120 ohm resistance could be interfering with the clock signal to our PHY. I'd suggest lowering to around 20 ohms.

3. Are there any pin-to-pin alternatives to your magnetics (48F-76NWZ2NL) that fit within our datasheet specs? Like I mentioned in my private message, this part falls outside of the datasheet specs for this PHY. I'm unable to find that part datasheet, so I'm basing this on a previous design that uses the same part:

Best,

Shane

Hi Shane-san,

Thank you for your prompt reply.

For item 1, please confirm that the same function as DP83869 exists in the register of DP83867.
For item 2 and item3, I have already reported items 2 and 3 to our customer. So, I will confirm with the customer whether they can try them or not.

Best regards,
Kato

Hi Kato-san,

1. Yes, the same register exists for the DP83867. Please set this to '0' to disable the automatic entry of legacy mode when the DP83867 is in master mode.

For more context on this mode:

- Legacy scrambler mode changes the scrambler settings and will prevent communication between the DP83867 and standard link partners.

- It was designed to support a few older ethernet PHYs that did not conform to the standard link up negotiation procedure.

- The DP83867 will automatically fall back to this mode if it struggles to maintain a link in master mode.

2/3. Thanks for passing this along to the customer. We only validate these parts to work within the datasheet specs, so we cannot guarantee functionality if the datasheet specs are violated.

Best,

Shane

Hi Shane-san,

Thank you for your information.

I will give feedback to our customer about the legacy scrambler mode. They will probably ask additional questions, so I would appreciate your continued support.

Best regards,
Kato

Hi Shane-san,

Thank you for your continuous support.

The customer is studying about the specification of the transformer and the damping resistance of the clock buffer, so I will report when there is an update.
Additionally, the customer are testing by setting 0x50 bit 1 to '0'. We'll get the results tomorrow.

By the way, what triggers the selection of legacy scrambler mode? We had the meeting with the customer today, but we were unable to explain the cause of the transition to legacy scrambler mode in master mode.

I would appreciate your cooperation.

Best regards,
Kato

Hi Kato-san,

Sadanori Kato said:

Additionally, the customer are testing by setting 0x50 bit 1 to '0'. We'll get the results tomorrow.

The register you should set is 0x14h bit 2, not 0x50 bit 1. The 0x50 bit 1 register is only relevant when the DP83867 is in slave mode. In master mode, this will likely not have any effect.

Sadanori Kato said:

what triggers the selection of legacy scrambler mode?

The PHY can revert to legacy scrambler mode if it has trouble bringing up the link in normal mode. I suggest trying to interfacing with the STB using the DP83867 EVM. We've tested that this EVM works, so doing this can help determine whether this is a DRX board related issue or a device related issue

Best,

Shane

Hi Shane-san,

Sorry for confusing you.

The above is a typo. Actually the customer is testing by setting 0x14 bit 2 to '0'. I understood that the workaround for master mode is 0x14 bit 2 and the workaround for slave mode is 0x50 bit 1 to avoid transition to the legacy scrambler mode. So, it turned out to be a lucky break.
Unfortunately I don't have the DP83867ERGZ-S-EVM. I will confirm if the customer has it. What are the possible causes if DP83867 has trouble bringing up the link in normal mode? I would appreciate it if you could give me some examples of possible causes.

Best regards,
Kato

Hi Shane-san,

The symptom wasn't replicated if setting 0x14 bit 2 to '0'. This seems like a workaround, but we haven't been able to figure out the root cause. The customer will test trying to interfacing with STB using DP83867ERGZ-S-EVM. If there is anything else we should try, any advice would be very helpful.

Best regards,
Kato

Hi Kato-san,

Sadanori Kato said:

What are the possible causes if DP83867 has trouble bringing up the link in normal mode?

Link troubles can stem from your magnetics, the MDI trace routing, return path, EMI, and more. One concern I have is that your magnetics are out of the datasheet spec.

Sadanori Kato said:

If there is anything else we should try, any advice would be very helpful.

I suggest extensive testing between the DRX and the STB using this workaround. If the issue is entirely gone, then the PHY may have been switching into legacy mode without actual link issues. I would appreciate if you can keep me updated on how this testing goes.

Best,

Shane

Hi Shane-san,

As a result of applying the workaround of setting 0x14 bit 2 to '0' between the DRX and the STB, the link was continued establishing and STB responded to all ping requests. As you feared, the DP83867IS may have been switching into legacy scrambler mode from normal scrambler mode without actual link issues. I had assumed that there would be cases where it would not respond to ping requests, but my guess was wrong. Then, could you please explain the detailed detected method of the transition to legacy scrambler mode in master mode?
I asked the customer again, but he didn't have the EVM. So, I would like to confirm just in case, but should customers purchase DP83867ERGZ-S-EVM?
Additionally, have you had similar link troubles in the past using same magnetics (48F-76NWZ2NL)?

Best regards,
Kato

Hi Kato-san,

Sadanori Kato said:

could you please explain the detailed detected method of the transition to legacy scrambler mode in master mode?

I'll need to look into this internally. I will be out of office until mid next week, so will ask my colleagues to help drive this until then.

Sadanori Kato said:

I would like to confirm just in case, but should customers purchase DP83867ERGZ-S-EVM?

This is really up to the customer. The EVM can be a good benchmark for performance and a reference for how to implement the DP83867. If the customer is satisfied that their board works, they may not need to test with the EVM. 

Sadanori Kato said:

Additionally, have you had similar link troubles in the past using same magnetics (48F-76NWZ2NL)?

I've only seen the linked E2E thread from my previous reply. They used the same magnetics and were failing some items on a LAN test. You can read through that thread for more details.

Best,

Shane

Hi Shane-san,

Thank you for your information.

For the detailed detected method of the transition to legacy scrambler mode in master mode, I am looking forward to hearing an update from your colleagues soon.
For legacy scrambler mode, I found "3.22 Non-compliant inter-operability mode" on page 48 of DP83865 data sheet. I think it's probably the same function. So, if you could tell me the details, I would be very grateful.

I will discuss with our customer whether they should purchase the DP83867ERGZ-S-EVM.

Best regards,
Kato

Hi Kato-san,

Shane-san is currently out of office, and will return on 3/5/25. He will answer your question then. 

Thank you.

Best,
J

Hi J-san,

Thank you for your prompt reply.

I understand.

Hi Shane-san,

I would like to confirm just in case, but is my understanding correct that the EVM can check any registers using USB-MDIO interface after the auto negotiation is completed without connecting MAC I/F?

Best regards,
Kato

Hi Kato-san,

Shane-san is currently out of office and will return 3/5/2025 to answer your question. Thank you.

Best,
J

Hi Shane-san,

The damping resistor connected to the output of the clock buffer was changed from 120Ω to 33Ω, but the symptom was replicated.

Best regards,
Kato

Hi Kato-san,

Shane-san is currently out of office and will return 3/5/2025 to answer your question. Thank you.

Best,
J

Hi Kato-san,

Sadanori Kato said:

For the detailed detected method of the transition to legacy scrambler mode in master mode, I am looking forward to hearing an update from your colleagues soon.

After discussing internally, the DP83867 will attempt to link in both normal and legacy modes by default. The PHY resolves to whichever mode it can achieve a link in. The only PHYs that should be able to link with DP83867 in legacy mode are older Broadcom PHYs, so I'm not sure why your STB would put the 867 into this mode. The first place I would check is your magnetics being out of spec. If you can test with different magnetics that fit our spec, that would be good to see.

FYI there is no risk with disabling legacy mode. If the customer is able to disable this mode, then the functionality should be ok.

Sadanori Kato said:

For legacy scrambler mode, I found "3.22 Non-compliant inter-operability mode" on page 48 of DP83865 data sheet. I think it's probably the same function. So, if you could tell me the details, I would be very grateful.

Yes I believe this is the same function as legacy mode. It is designed to support a link with older Broadcom PHYs that did not use the standard link up procedure:

Sadanori Kato said:

is my understanding correct that the EVM can check any registers using USB-MDIO interface after the auto negotiation is completed without connecting MAC I/F?

Yes that is correct. You do not need to connect a MAC interface to complete auto negotiation on the MDI side or to read our PHY registers through the MDIO lines. You will need an external MSP430 to interface using USB-MDIO as described on this webpage.

Sadanori Kato said:

The damping resistor connected to the output of the clock buffer was changed from 120Ω to 33Ω, but the symptom was replicated.

Thanks for checking this. It seems that the damping resistor is not the cause of this behavior.

Best,

Shane

Hi Kato-san,

Understood, I will keep watching this thread for future updates.

This will be good to check whether you're seeing a board-specific behavior or device-specific behavior. 

Best,

Shane

Hi Shane-san,

Thank you for your continuous support.

I will share updates with you when I get the test results.

Could you please tell me the part numbers of older Broadcom PHYs which can work in legacy scrambler mode?

Best regards,
Kato

Hi Kato-san,

Looking at the DP83865 datasheet, it seems that earlier revisions of BCM5400 would use legacy mode for linking up:

I'm not aware of other parts that use this method to link up.

Best,

Shane

Hi Shane-san,

Thank you for your information.

I overlooked that part in the DP83865 datasheet.
Would it be possible to disclose the detailed detected method of the transition to legacy scrambler mode in master mode to us?

Best regards,
Kato

Hi Kato-san,

Let me check internally on the legacy scrambler mode.

As for the STB link up question, its certainly possible that the Realtek PHY on the STB side is causing the link up issue. I would check with the manufacturer of that PHY to see whether they have seen this in the past.

Best,

Shane

Hi Shane-san,

Thank you for your information.

The customer received the DP83867ERGZ-S-EVM and MSP-EXP430 F5529LP today. I will let you know when the results are available.

Best regards,
Kato

Hi Kato-san,

Thank you for the update. I will await the results on the EVM testing.

Best,

Shane

Hi Shane-san,

The customer's automated test environment has not been fixed and the results will be reported after next week.

Best regards,
Kato

Hi Kato-san,

Understood, I will keep this thread open for any updates.

Best,

Shane

Hi Shane-san,

I will contact you if I receive any updates from the customer.

Best regards,
Kato

Hi Shane-san,

Unfortunately, the same issue has been replicated by connected between DP83867ERGZ-S-EVM and STB. Could you please check the register dump file which I sent via a private message?

Best regards,
Kato

Hi Kato-san,

From the register dump, I see the PHY is in master legacy mode and the link is not established like you've described. If this is on the EVM, it suggests the behavior is not tied to the customer's system and could be due to how the STB PHY is interfacing with our DP83867.

If it's ok with you, I can try to reproduce this behavior in our lab and look into what is causing it. Would the customer be open to sending a STB board to our Dallas site?

Best,

Shane

Hi Shane-san,

Thank you for your suggestion.

I will contact the customer to confirm if they can lend you the STB board and get back to you.

Best regards,
Kato

Hi Kato-san,

Sounds good, I will await your reply.

Best,

Shane

Hi Shane-san,

Please see my reply on a private message.

Best regards,
Kato

Hi Kato-san,

I included my shipping details in our direct message. If the customer can ship the STB here that would be best.

Best,

Shane

Hi Shane-san,

Thank you for your continuous support.

We are currently discussing with the customer regarding the shipping, so please wait a little while longer.

Best regards,
Kato

Hi Kato-san,

I will await your reply. Let me know if you need anything else on my end.

Best,

Shane

Hi Shane-san,

Thank you for your support.

Please see my reply on a private message. I will contact you if there are any updates.

Best regards,
Kato

Thanks Kato-san,

I've replied to your private message. If you can elaborate on the 'second symptom' between the EVM and STB that would be good to know.

Best,

Shane

Hi Shane-san,

Sorry for confusing you.

The second symptom isn't a new issue.
This issue may be low reproducibility, so it may take some time for you to reproduce it.

Best regards,
Kato

Hi Kato-san,

I will try to reproduce the issue in our lab. My understanding is this behavior appears less than 1/500 times.

Like you say, I want to set the expectation that this will take time to reproduce.

Best,

Shane