• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 33 subscribers
  • Views 237 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

DP83TC812R-Q1: RGMII Timing setting

DP83TC812R-Q1: RGMII Internal delay setting

Jing Liang
Prodigy 160 points
Part Number: DP83TC812R-Q1

Tool/software:

I plan to set internal delay for 100base T1 RGMII and TX and RX delay shall be set at PHY side.

  1. If align mode is used during strap setting, and  cfg_rgmii_rx_clk_shift_sel=1b  cfg_rgmii_tx_clk_shift_sel=1b

what is the RGMII internal delay of TX and RX? only 2 ns? datasheet shows only 2ns.

  1. If  RGMII (TX and RX Internal Delay Mode) is used during strap setting, 
    What is the RGMII internal delay of TX and RX? 5 ns? because default setting of below register setting:

dll_tx_delay_ctrl_rgmii_sl: 0xFh(5ns);
dll_rx_delay_ctrl_rgmii_sl: 0xFh(5ns);

  1.  cfg_rgmii_rx_clk_shift_sel  cfg_rgmii_tx_clk_shift_sel describe if set to 1b then there is 90 degree between clk and data.
    1. if RGMII align mode used, then the TX and RXD internal delay is 10ns?
    2. if RGMII (TX and RX Internal Delay Mode) is used, then the TX and RXD internal delay is 15ns?
  • 0
    TI__Genius 9209 points

    Hi Jing,

    Thank you for clarifying your previous questions:

    Jing Liang said:
    1. If align mode is used during strap setting, and  cfg_rgmii_rx_clk_shift_sel=1b  cfg_rgmii_tx_clk_shift_sel=1b

    what is the RGMII internal delay of TX and RX? only 2 ns? datasheet shows only 2ns.

    Yes, 2 ns because the register value overrides the strap setting.

    Jing Liang said:

    dll_tx_delay_ctrl_rgmii_sl: 0xFh(5ns);
    dll_rx_delay_ctrl_rgmii_sl: 0xFh(5ns);

    No, if you were to set [11:8] and [7:4] to 0xFh the resulting delays would be 5ns. The default delay for each is 2.5ns.

    Jing Liang said:
    cfg_rgmii_rx_clk_shift_sel  cfg_rgmii_tx_clk_shift_sel describe if set to 1b then there is 90 degree between clk and data.

    See an updated datasheet. www.ti.com/.../dp83tc812r-q1.pdf

    Jing Liang said:
    if RGMII align mode used, then the TX and RXD internal delay is 10ns?

    Align means -750ps to 750ps on RX and no added delay on TX.

    Best,

    Nick

  • 0 in reply to Nick Peabody
    Prodigy 160 points
    Nick Peabody said:
    f

    If there is MAC align mode +PHY TX shift mode(assume 2.5ns), what is below requirement of setup time and hold time? still keep min value 1ns? BTW below requirement is at PHY PIN or internal? Can I add 2.5ns for both min and Tpy for the receiver requirement of setup time and hold time? 

  • +1 in reply to Jing Liang
    TI__Genius 9209 points

    Hi Jing,

    The requirement is a minimum amount of time:

    A minimum of 1ns setup and 1ns hold time must be maintained at the input of the receiver. 

    We add delay in order to exceed to minimum. The issue would be if the amount of time between TX and RX is less than 1 ns. 

    Jing Liang said:
    still keep min value 1ns? BTW below requirement is at PHY PIN or internal?

    yes, internal or PHY pin, the difference is small. 

    Jing Liang said:
    Can I add 2.5ns for both min and Tpy for the receiver requirement of setup time and hold time?

    No, because the 1 ns value comes from the RGMII input timing specifications. Adding delay has no impact on specifications that are constant.

    Best,

    Nick