SN65DSI83: Setting for LVDS CLK from REFCLK

Hi Hirobe-san,
I will review the information, and get back to to you shortly. 

Best,
J

Hi, J san,
thank you for your reply and I tried it.

0x0A are 0x00 and ....
these are my results. 

 setting           LVDS OUT CLK
0x0B=0x00 = 80Mhz
0x0B=0x01 =100Mhz
0x0B=0x02 =100Mhz
0x0B=0x29 =16.7Mhz
0x0B=0x2A =16.7Mhz

freq_change20250305.csv

Hi Hirobe-san,

I noticed in the csv file that the value for 0x0A changes, not 0x0B. 

Could you verify that register 0x0B was changed, not 0x0A?


Also, when you select REFCLK to output LVDS_CLK, you cannot change the value of 0x0B[7:3] from 0b00000 so 0x29 and 0x2A for 0x0B will not be a valid value to guarantee proper behavior of the chip. 




Best,
J

Hi J san
Thank you for your reply.

>Could you verify that register 0x0B was changed, not 0x0A?
I confirmed my setting was correct. 

This setting occurs this result.

 
 setting           LVDS OUT CLK
0x0B=0x00 = 80Mhz
0x0B=0x01 =100Mhz

But I understand that I must keep 0x0B[7:3]=0b00000.

And for getting 27MHz LVDS OUT, I need to change REFCLK to 27Mhz, for example, right? 

freq_change20250306.csv

Hi Hirobe san,

Yoshifumi Hirobe said:

And for getting 27MHz LVDS OUT, I need to change REFCLK to 27Mhz, for example, right? 

Because 0x0B[1:0] is REFCLK_MULTIPLIER, if your REFCLK is 100 MHz, it will not be possible to decrease your LVDS_OUT_CLK to 27 MHz. 
So, to get 27 MHz LVDS OUT, REFCLK should be 27 MHz with 0x0B=0x00. 

Yoshifumi Hirobe said:

0x0B=0x00 = 80Mhz

It is still weird that LVDS OUT is 80 MHz when REFCLK is 100 MHz. 
However, this could be because of 0x0A[3:1] which is the register that sets LVDS_CLK_RANGE. If this is currently set to 0x0A[3:1] = 0b000, this may cause unexpected behavior. 

Best,
J

J san
Thank you for your reply.

I can't understand why 80Mhz is out, too.
I will get 27Mhz Oscillator next week, and I will check again.

Hirobe san, 
I will also discuss internally to see how it can happen and update you.
Please let me know how it goes. 

Thank you.

Best,
J

Hi Hirobe san,
I followed up internally and they suggest to change the LVDS_CLK_RANGE to see if LVDS_CLK will output 100 MHz given 100 MHz REFCLK with x1 multiplier. 
Note that if multiplier creates LVDS_CLK exceeding 154MHz, there will be undefined behavior on LVDS_CLK. That explains the 16.7 MHz that LVDS_CLK sees when the multiplier goes beyond 2.

To answer the initial question, the best way to output 27 MHz on LVDS_CLK would be to use REFCLK lower than 27 MHz and multiply REFCLK to make LVDS_CLK 27 MHz. 
For example, 
REFCLK = 27 MHz, multiplier = 1, LVDS_CLK = 27 MHz

REFCLK = 9 MHz, multiplier = 3, LVDS_CLK = 27 MHz 

Please let me know how it goes on your end. 

Best,
J