• State TI Thinks Resolved
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 31 subscribers
  • Views 22 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

TCA6424A: I have a question about the reset timing requirements for the TCA6424A.

user6448843
Prodigy 120 points
Part Number: TCA6424A

Tool/software:

I have a question about the reset timing requirements for the TCA6424A.

The relevant parts of the datasheet are "6.7 Reset Timing Requirements" and "Figure 7-4. Reset Load Circuits and Voltage Waveforms".

Could you please elaborate on when the reset requirement needs to be respected?
(Could you please explain in detail about the timing of each of the items in the red boxes below (① to ⑤)?)

Best regards

  • 0
    TI__Mastermind 37293 points

    Hi User6448843,

    tW = RESET pulse duration. This is the time needed to hold /RESET below a VCCP/2 voltage for a valid /RESET pulse. The width of the pulse needs to be at least 4 ns in length for it to be considered a valid /RESET pulse. Anything faster than this, and the reset condition may not be recognized by the I/O expander. 

    tREC = RESET recovery time. After a successful reset condition is given (high-low-high on /RESET pin), there exists some time before an I2C start condition can be issued. In this case, the tREC = 0 ns, so after a reset condition, a start condition can immediately occur. 

    tRESET = Time to RESET. In the graph, the example is if SDA is held LOW or an I/O (Pn) is held LOW/HIGH, at what time will the I/O expander reset back to its default state. On the falling edge of /RESET being toggled, you need at least 600 ns of time to see Pn or SDA go back to their initial conditions. 

    Please let me know if you have any additional questions.

    Regards,

    Tyler