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Original question:

SN65DSI86: Use DSI CLK vs. the Ref CLK

SN65DSI86: question about SN65DSI86

Jimmy Huang
Genius 3535 points
Part Number: SN65DSI86

Tool/software:

Hello:

The customer's screen display requirements are as follows. May I ask if it is necessary to connect two DSIs to complete the requirements? Is it possible for the customer to only connect one DSI route? Thank you

  • 0
    TI__Genius 13390 points

    Hi Jimmy,

    Do you know the blanking for the Horizontal/Vertical parameters?

    Best Regards,

    Gil Abarca

  • 0 in reply to Gil Abarca Ramos
    Genius 3535 points

    Hello Gil：

    This is the information provided by the screen supplier

    vclk = 240MHz htotal = 2426 hstart = 12 hwidth = 2266 vtotal = 1649 vstart = 129 vheight =1488 hsw = 8 vsw = 2

    please help check，May I ask if it is necessary to connect two DSIs to complete the requirements? Is it possible for the customer to only connect one DSI route? Thank you！！！

  • 0 in reply to Jimmy Huang
    TI__Genius 13390 points

    Hi Jimmy,

    This is resolution is supported with one DSI port.

    Best Regards,

    Gil Abarca

  • 0 in reply to Gil Abarca Ramos
    Prodigy 10 points

    Hi Gil,

    Could you tell us how to check or calculate  the resources supported by SN65DSI86  chip in one DSI port mode（4lane） ?

    otherwise, how to check what resolution image size is supported by one DSI port（4 lane）  ? 

     what frame rate range is supported in SN65DSI86 chip ？

    Best Regards,

    shuliang

  • 0 in reply to li shuliang
    TI__Genius 13390 points

    Hi Li,

    li shuliang said:

    Could you tell us how to check or calculate  the resources supported by SN65DSI86  chip in one DSI port mode（4lane） ?

    otherwise, how to check what resolution image size is supported by one DSI port（4 lane）  ? 

     what frame rate range is supported in SN65DSI86 chip ？

    This chip is not video resolution dependent is based on bandwidth. Based on the resolution and frame rate we can calculate the bandwidth the resolution requires.

    The video bandwidth requirement is calculated as follows: 

    PCLK = HTotal x VTotal x fps

    Video Bandwidth Requirement = PCLK x bpp

    In this case the video bandwidth requires 240MHz x 24bpp = 5.76Gbps

    For the SN65DSI86 bridge chip the DSI bandwidth available is: # Lanes x supported bandwidth

    The max data rate per lane is 1.5Gbps x 4 lanes = 6Gbps available.

    Now, for the DP output there is an encoding in the DP protocol which is 8/10. The available bandwidth for the DP output is: #Lanes x data_rate x 8/10. For this resolution you can configure the DP output to 4 Lanes x 2.7Gbps x 8/10 = 8.64Gbps. 

    Hope this helps!

    Best Regards,

    Gil Abarca