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Original question:

SN65MLVD206B: SN65MLVD206B load and output level

SN65MLVD206B: About input during power-off

SHUNSUKE IDE
Prodigy 10 points
Part Number: SN65MLVD206B
Other Parts Discussed in Thread: TRS3122E, STRIKE

Tool/software:

Hello,
We are designing the SN65MLVD206B in receiver mode, and if there is some input on A and B (pins 6 and 7) while the power is off, is there a possibility of failure due to overcurrent or other reasons?
In our analysis, it seems that pins 5 and 8 of the SN65MLVD206B are shorted.
We think the cause is due to a mistake in the order of power input.

  • 0
    Guru 316760 points

    The absolute maximum ratings allow voltages up to 4 V at all times.

    I suspect that you have overvoltage, i.e., < −1.8 V or > 4 V, due to ESD or transients. How are the inputs and the supply protected?

  • 0 in reply to Clemens Ladisch
    Prodigy 10 points

    Thank you for your response.

    Regarding the 3.3V supply, it is provided from a regulated power source with a current limit applied. However, there was no current limit applied to the 12V supply. The 12V passes through the same board (Board 1) and is supplied to an external board (Board 2). On Board 2, M-LVDS signals are output towards Board 1 and received by an M-LVDS receiver.

    We suspect that the failure occurred because we supplied 12V before supplying the 3.3V for Vcc. However, if the absolute maximum ratings are valid even without Vcc being supplied, then this scenario seems unlikely.

    The TRS3122E is also implemented on the same board. Does the absolute maximum rating specified in the datasheet for the TRS3122E also apply to situations where Vcc is not supplied?

  • 0 in reply to SHUNSUKE IDE
    Guru 316760 points

    I was asking if the LVDS lines are protected against voltages > 4 V, or if the 3.3 V supply is protected against voltages > 3.3 V.

    All absolute maximum ratings apply to the specified test conditions. If VCC is not mentioned, then the values are indepedent from the power-on state.

  • 0
    TI__Expert 3170 points

    Hi,

    As Clemens has said, the absolute maximum ratings are valid even during power off. Could you please share your schematic? What exactly is the failure you are seeing?

    Regards,

    Jack

  • 0 in reply to Jack Campbell
    Prodigy 10 points

    Hello,
    Thank you for your response.

    We think that the 3.3V power supply, being regulated, will not exceed 3.3V.
    Although there is no high-voltage protection circuit for the LVDS lines, the design ensures that inputs exceeding the absolute maximum ratings are not applied. If input during power-off does not cause any issues, we think that there might have been some incorrect input in our evaluation environment. (For example, 12V might have been applied to an input pin.)

    We will attach a simple block diagram.

  • 0 in reply to SHUNSUKE IDE
    Guru 316760 points

    Can any of these signal lines be touched (resulting in ESD)? Can these connection be hot-plugged (resulting in arcing)?

  • 0 in reply to SHUNSUKE IDE
    TI__Expert 3170 points

    Hi,

    It sounds like the failure could be a result of a misapplied input like you mention or an ESD strike. Has this failure only occurred on one board or across many? If it is an isolated failure I would replace the chip and ensure proper functionality afterward.

    Regards,

    Jack