TCAN4550-Q1: Delays Observed in CAN message transfer

Hi Jonathan,

Yes, it's about throughput issues, like when we do a single CAN transfer, we get around 7.5k msg/sec, but if we do 2 CAN simultaneous transmissions, we get in each CAN around 4k msg/sec, but we want both to have 7.5k in this case too.

Also, we did an SPI dev test for checking the SPI alone performance without any CAN transceiver connected, and we found that the timings during the single SPI transfer and both SPI simultaneous transfers were the same, so for this simultaneous situation, SPI has the capacity to transfer those, which it had done in a single transfer. Also, asking about this situation with our processor side, they are saying that it depends on how the driver is designed to handle multiple devices.

So, is there any suggestion that you can give to help us resolve this?

Thank you!

Regards,

Ankita

Hi Ankita,

While you haven't directly confirmed this, it sounds like the processor can only service one TCAN4550 through SPI at a time.  If a single device can transfer 7.5k msg/sec, and the total combined msg/sec for two devices is about the same when a second device is added, and each device has about half the message count.

To maximize CAN message throughput, you need to optimize the SPI communication and reduce as much idle time and unnecessary bits as possible.

• Maximizing the SPI bit rate reduces the bit period and shortens the total time of each SPI transaction
• Use Multi-Word SPI Read/Write transactions whenever possible to reduce the number of 32-bit word SPI Headers (read/write op code + address + Length)
• Reduce the idle time between SPI transactions
• Reduce or eliminate any idle time within the SPI transaction.
  • The time between the Chip Select falling Low and the start of the SCLK/Data
  • The time between the last SCLK/Data bit and the Chip Select rising High
  • Any time within the SCLK/Data portion that comes from a processor or driver only being able to process a reduced number of bits such as 8 or 16 bits at a time.  The TCAN4550 operates on 32-bit words and each SPI transaction is a minimum of 64-bits
• Eliminate any unnecessary SPI register or MRAM activity.  Use the features you need, but eliminate features you don't.  For example, if you don't actually use the TX Event FIFO for keeping track of transmitted messages, then don't configure it for use which would only require additional SPI activity to process and service this FIFO and any interrupts associated with it. etc.
• Using the Multi-Word SPI Read/Write feature also allows multiple CAN Message RX/TX buffers in consecutive memory to be processed in a single very long SPI transaction.  For example, setting a RX FIFO Watermark level would allow you to read multiple RX message buffers at a time and then issuing a single SPI Write to acknowledge all of the messages have been read instead of individually reading and acknowledging every single RX message.

I hope these are helpful suggestions on how to approach optimizing performance.

Regards,

Jonathan

Hi,

Jonathan Nerger said:

f a single device can transfer 7.5k msg/sec, and the total combined msg/sec for two devices is about the same when a second device is added, and each device has about half the message count.

Does it mean like whatever the single CAN throughput is, if we add another CAN, both together will give what's given by single CAN, and in each it will be half?

Regards,

Ankita

No, I'm just looking at your numbers about what you are reporting the processor is capable of doing.  The TCAN4550's operate independently of each other and will transmit messages on the CAN bus according to the rules of arbitration whenever the processor loads a message into a TX buffer element and sets the corresponding bit in the TXBAR register to initiate the transmission.

There might be two limiting factors:

1. The Processor may not be able to service both TCAN4550 devices through the separate SPI interfaces at full rate which may result in a reduction of the overall CAN message throughput for each TCAN4550 device.
2. The CAN bus loading may start to become saturated and the rules of arbitration may start to limit the total number of messages each TCAN4550 can transmit because it now has to arbitrate with an additional TCAN4550 device also trying to transmit on the bus simultaneously.

I can't speak definitively about your processor, but generally speaking two TCAN4550's will double the work required by the processor and could lead to a decrease in CAN message throughput.

Likewise adding a second TCAN4550 and expecting it to also transmit 7.5k msg/sec will mean that the CAN bus will need to support 15k msg/sec, or the CAN protocol will become a limiting factor.  The maximum number of CAN messages that can be supported will vary with the bit rates, and data length fields for each message.  Does your CAN bus have enough bandwidth or margin to support 15k msg/sec?  If not, then this might explain your reduced msg/sec rate for each TCAN4550 device.

Regards,

Jonathan