DP83867IR: How to configure the register in PHY

Saranraj N

Part Number: DP83867IR
Other Parts Discussed in Thread: MSP430F5529, , USB-2-MDIO, DP83TC812EVM-MC

Tool/software:

Hi TI Team,

I am planning to use the DP83867IRPAP Ethernet PHY connected to the GMAC block in our SoC via the GMII interface to perform 1000BASE-T compliance testing. As part of this setup, I need to configure specific registers within the PHY to enable compliance test modes and other relevant features.

Could you please advise on the recommended method to configure these registers? Additionally, is there any software tool available to interface with the PHY and perform register-level configuration (e.g., via MDIO)?

Regards,

Saran

over 1 year ago

0 Gerome Cacho over 1 year ago

TI__Mastermind 44855 points

Hi Saran,

Please see SNLA239 for this information on how to configure. We do offer USB2MDIO to program registers using a MSP430F5529 Launchpad if you have this available.

Sincerely,

Gerome

0 Saranraj N over 1 year ago in reply to Gerome Cacho

Prodigy 40 points

Hi Gerome Cacho,

    Thank you for the information you previously shared.it has helped clarify the PHY register configuration process. I still have a few follow‑up questions:

From my understanding, the following items are essential for configuring the DP83867IR:
     - MSP‑EXP430F5529LP
     - MSP430 USB drivers
     - USB‑2‑MDIO Software Tool
1) Could you please confirm that these are the only components needed for PHY register access? or any additional items are needed?

2) Could you kindly provide a Exact jumper positions required when the MSP430F5529 is used as a USB‑to‑MDIO bridge & detailed user guide for the MSP430F5529 LaunchPad.

Regards,

Saran

0 Saranraj N over 1 year ago in reply to Gerome Cacho

Prodigy 40 points

Hi Gerome Cache

For Ethernet compliance testing, I follow the setup: GMAC pins → DP83867IR (PHY chip) → RJ45 connector. As you said earlier, the MSP430F5529 LaunchPad is used to configure the PHY registers via MDC and MDIO. The USB-2-MDIO tool is used for register configuration. In this setup, pin P4.2 of the MSP430F5529 is connected to the PHY’s MDC pin, and P4.1 is connected to the MDIO pin. I have a doubt—does P4.2 of the MSP430F5529 provide a 25 MHz clock to the PHY's MDC pin?

0 Gerome Cacho over 1 year ago in reply to Saranraj N

TI__Mastermind 44855 points

Hello,

If using the launchpad, please ensure that the MSP is flashed with FW specific to USB2MDIO. In addition, MDC is actually P4.1 while MDIO is P4.2. The MSP will provide the MDC as needed, and will not be free-running.

I have attached a .ppt and FW file in case.

How to flash MSP430 Launchpad for USB2MDIO compatibility.pptx 8053.msp430-usb-to-mdio-universal-v3.04.txt

Sincerely,

Gerome

0 Saranraj N over 1 year ago in reply to Gerome Cacho

Prodigy 40 points

Hello Gerome Cache,

Thank you for the clarification. As per the SNLU197 document, on page 5, it is stated that P4.1 as the MDIO pin and P4.2 as the MDC pin. Could you please confirm and clarify this assignment?

0 Gerome Cacho over 1 year ago in reply to Saranraj N

TI__Mastermind 44855 points

Hello,

This is a typo. Please proceed with instructions per .ppt.

Sincerely,
Gerome

0 Saranraj N over 1 year ago in reply to Saranraj N

Prodigy 40 points

Hi Gerome Cache,

We are in the process of selecting a compatible RJ45 connector with integrated magnetics for 1000BASE-T compliance testing.

Despite reviewing numerous options, we have not yet found a connector that fully meets the specifications outlined in the DP83867IRPAP datasheet. Could you please recommending a suitable RJ45 connector with integrated magnetics that is verified or known to work reliably with this PHY.

This will help us ensure reliable compliance testing and proper integration of the PHY.

0 Gerome Cacho over 1 year ago in reply to Saranraj N

TI__Mastermind 44855 points

Hello,

Please take a look at our DP83TC812EVM-MC and DP83TC720EVM-MC for examples on integrated magjack.

Sincerely,

Gerome

0 Saranraj N over 1 year ago in reply to Gerome Cacho

Prodigy 40 points

Hello Gerome Cache,

Thank you for the valuable information shared earlier. Could you kindly provide further insights regarding the required input data or patterns on the TXD pins from the GMAC to the PHY during Test Modes 1, 2, 3, and 4 as specified in the 1000BASE-T compliance testing.

Regards,

Saran

0 J over 1 year ago in reply to Saranraj N

TI__Mastermind 26771 points

Hi Saran,

Test mode signals are generated by the PHY by configuring the register via USB2MDIO according to SNLA239 that Gerome linked earlier in the post. There are no required input data or pattern from the MAC side.

Best,
J

0 Saranraj N over 1 year ago in reply to J

Prodigy 40 points

Hi J,

/resized-image/__size/640x480/__key/communityserver-discussions-components-files/138/3782.TEST_5F00_SETUP.PNG

Our requirement is to perform compliance validation for the GMAC with GMII interface. To facilitate this, we have externally connected a PHY device to the GMAC(Refer attached link). As per your previous inputs, the PHY is capable of generating the required patterns/data independently for the 1000BASE-T compliance test, and direct involvement from the GMAC is not necessary. In this context, I would like to understand, What role does our SoC (which includes the GMAC block) actually play during the compliance testing phase?

Regards,

Saran

0 J over 1 year ago in reply to Saranraj N

TI__Mastermind 26771 points

Hi Saran,

1000Base-T compliance test does not require any configuration on the SoC end. Please refer to https://www.ti.com/lit/pdf/snla239.

Best,

Interface

Interface forum

DP83867IR: How to configure the register in PHY