SN65DSI83: any display. Please support us.

Yoshifumi Hirobe

Part Number: SN65DSI83
Other Parts Discussed in Thread: DSI-TUNER

Tool/software:

We are creating our own printed circuit board, outputting MIPI from a device called i.MX8, and attempting to perform LVDS conversion for an LCD monitor.

3 months ago

0 Ragav Subramanian 3 months ago

TI__Expert 3377 points

Hi Yoshifumi,

A few follow-up questions:

Are you using DSI-tuner to configure the device?
Can you share MIPI DSI settings from MX8?
- datarate, lane count and resolution?

Since reg 0xE5 is showing 0x80 VS/HS sync error - please start by checking the VS/HS sync polarity of your LCD monitor(not shown in table) and ensure it matches with the register setting in 0x18.

Thanks,

Ragav Subramanian

0 Yoshifumi Hirobe 3 months ago in reply to Ragav Subramanian

Prodigy 80 points

Hi Ragav-san

・No, I didn’t use DSI-tuner.
I saw that this file was mentioned in E2E, but I couldn't install it.
　SN65DSI83ZXHR: unable to reset the LVDS bridge through software and no output on display - Simulation, hardware & system design tools forum - Simulation, hardware & system design tools - TI E2E support forums

・MIPI DSI settings from i.MX8

CLK 163MHz

lane count 2

resolution 800 x 480

horizontal 800 + 44 + 2 + 14

vertical 480 + 38 + 2 + 8

・The VS/HS sync polarity of LCD

0 Yoshifumi Hirobe 3 months ago in reply to Yoshifumi Hirobe

Prodigy 80 points

I changed it and I can display LCD.
CHA_SYNC_DELAY_LOW　0x00　-> 0x21

Please tell me what values this setting should have and how I should evaluate them.

0 Ragav Subramanian 3 months ago in reply to Yoshifumi Hirobe

TI__Expert 3377 points

Hi Yoshifumi,

Glad to hear the system is operating now.

The CHA_SYNC_DELAY_LOW　0x00　-> 0x21 is the additional delay in the device for outputting H/Vsync High to Low transition. The CHA_SYNC_DELAY_LOW and CHA_SYNC_DELAY_HIGH registers must be greater than 32 per the datasheet. The 0x21 passes this requirement and allows the appropriate delay for the output - please ensure CHA_SYNC_DELAY_HIGH is also within the requirement

Thanks,

Ragav Subramanian

0 Yoshifumi Hirobe 3 months ago in reply to Ragav Subramanian

Prodigy 80 points

Hi Ragav-san

Thank you for your answer.
Regarding the register setting value,
Currently it's working fine with 0x21, but could you please advise on how to fine-tune it, such as using 0x22 or 0x23...etc, and what specific adjustments should be made?

0 Ragav Subramanian 3 months ago in reply to Yoshifumi Hirobe

TI__Expert 3377 points

Hi Yoshifumi-san,

The minimum requirement for the register is 0x20 (32 pixel clocks delay).

I would advise the following criteria to use as a rough guideline to find appropriate delay values:

If VSYNC/HSYNC toggling too early or not toggling -> increase delay
- if issue with rising edge -> increase DELAY_HIGH
- if issue with falling edge -> increase DELAY_LOW
If VSYNC/HSYNC toggling too late (after video data completion) -> decrease delay
- if issue with rising edge -> increase DELAY_HIGH
- if issue with falling edge -> increase DELAY_LOW

Once a working value is found, I would not expect much variation in value needed; however, the customer can run some longer stress tests and POR testing to ensure the setting is robust.

Thanks,

Ragav Subramanian

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