DS90UB954-Q1: DS90UB954 Schematic review

Hi Dilip,

Here is my feedback on the schematic.

• Capacitor on RIN0- and RIN1- should be 47nF. This is because capacitance on + and – pins need to be matched, and RIN+ traces include two 100nF capacitors in series = 50nF total capacitance. (100nF AC coupling capacitors at DES pin and SER pin.)

• The PoC network shown appears similar to the network recommended in the datasheet, however some component values and part numbers differ. Additionally the network recommended in the datasheet cannot be used in this application because it supports a frequency range of 25MHz – 2.1GHz.
  • Since non-synchronous mode is used, the back channel rate is 10Mbps. Since the reference clock frequency is 25MHz, the forward channel rate is 4Gbps. Therefore the frequency range of the channel which needs to be supported by the PoC network is 5MHz – 2GHz.
  • It is recommended to select an example network from app note SNLA224A which supports the frequency range 5MHz – 2GHz. Make sure to use all component values and part numbers exactly as shown in the app note.
  • If you do not wish to use a network provided in the app note, simulations will need to be performed at the schematic and layout stages of your design to ensure the custom PoC network meets all requirements provided in the FPD3 Channel Specification document. Please let me know if you do not already have access to this document.

• VDD11 supply pins are decoupled with 4.7uF, 10nF, and 100nF capacitors. Either the 10nF or the 100nF capacitor can be removed.
• VDD18_CSI supply pin is decoupled with 10uF, 100nF, and 10nF capacitors, Ether the 10nF or the 100nF capacitor can be removed.

Additionally I have a few questions.

• Which serializer will be paired with the 954 in this application?
• Can you share the name of the customer for my information?

Best,

Lucas