Tool/software:
Hello,
We are using the TI DP83867E PHY in SGMII mode. The PHY is implemented on an FMC board and interfaces with a Xilinx Zynq FPGA running embedded Linux.
We are experiencing an intermittent issue: the PHY is only detected by Linux approximately 9 times out of 10 after a reboot, whether or not power is fully cycled. When the issue occurs, the MDIO interface is not accessible, and the PHY appears completely unresponsive.
The reset signal is released well after all power rails are stable. The power rails are as follows:
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VDDIO: 3.3V
-
VDDA2P5: 2.5V
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VDDA1P0: 1.0V
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VDDA1P8: not used
We have reviewed the datasheet and found no specific constraints related to power sequencing. Once the PHY is properly detected, the SGMII link is stable and performs well.
Any insights or suggestions would be greatly appreciated.
Thank you!
Sébastien