DS125DF410: Request for Technical Support on DS125DF410 Configuration.

Hi Tatsumasa-san,

Thanks for the detailed background on your system and what you are trying to achieve.  You mentioned that ultimately you will use manual CTLE value identified in your study.  Is it possible to share more background on this?  I'm curious why you're choosing this over automatic adaptation.

Also, I would be interested to know more about what testing you will perform in order to confirm your selected CTLE value is optimal.

As I discussed in the other thread, to release CDR reset, I would recommend writing 0x10 to register 0x0A.  Beyond this, your register sequences are correct.

Tatsumasa Imai said:

First, is the following approach correct for Method 1?

Yes, this is correct.

Tatsumasa Imai said:

I am unsure whether the CDR Reset via register 0x0A mentioned in steps 3 and 5 is truly necessary.

CDR reset will force the retimer to re-adapt to the input signal.  We typically recommend performing CDR reset when changing receiver settings or CDR settings in order to force new adaptation.

Tatsumasa Imai said:

Next, is the following approach correct for Method 2? Please let me know if there are any other registers I should check or operate on.

Yes, this is also correct.

You might find registers 0x27 and 0x28 valuable.  These are HEO/VEO from the internal eye monitor.  We typically observe good BER for HEO >= 0.4UI, VEO >= 200mV.

Tatsumasa Imai said:

(Final settings: Set to Manual CTLE mode and apply the CTLE Gain value for Cable B obtained from the preliminary study.)

Setting register 0x2D is not required for DS1xxDF410 devices.  Other than this, your settings look good.

Thanks,

Drew

Hi, Drew-san,

Thank you for your response.
I would like to answer the questions you raised.

> I'm curious why you're choosing this over automatic adaptation.

In fact, I also believe that Automatic Adaptation is optimal.
However, since the transmission medium, Cable B, is always the same, I think that an optimized Manual CTLE can achieve transmission quality comparable to that of Automatic Adaptation. Additionally, because Cable B is frequently connected and disconnected, using Manual CTLE allows for relatively easier detection of Cable B's degradation by reading HEO/VEO values. Furthermore, since the system I inherited was originally using Manual CTLE, adopting it as is would minimize changes to the system.
Due to these multiple background factors, I am currently considering both Automatic Adaptation and Manual CTLE simultaneously.

> I would be interested to know more about what testing you will perform in order to confirm your selected CTLE value is optimal.

I plan to read Registers 0x27 and 0x28 while Cable B is connected. The evaluation will be based on how large the values of HEO/VEO are that I read.

Hi Drew-san,

In our system using the DS125DF410 in Manual CTLE mode, we performed the following steps for verification. The DS125DF410 is used as a receiving device.

(step A1) Connect the transmitting device and the receiving device with Cable A (approximately 4m).
(step A2) Write 0x0C to register 0xFF.
(step A3) Write 0x20 to register 0x31.
(step A4) Write 0x1C to register 0x0A.
(step A5) Wait for more than 40 usec.
(step A6) Write 0x10 to register 0x0A.
(step A7) Read register 0x03.

(step B1) Replace Cable A with Cable B (approximately 7m).
(step B2) Write 0x0C to register 0xFF.
(step B3) Write 0x20 to register 0x31.
(step B4) Write 0x1C to register 0x0A.
(step B5) Wait for more than 40 usec.
(step B6) Write 0x10 to register 0x0A.
(step B7) Read register 0x03.

As a result, there was no change in the values read at (step A7) and (step B7). I suspect that the change from Manual CTLE to Auto adaptation CTLE performed in (step A3) and (step B3) did not go well.

For reference, I will attach the values of all registers of the DS125DF410 read at (step A1) and the values of all registers read at (step A7). Is there any mistake in the configuration?

********************************************************

Hi Tatsumasa-san,

Thanks for sharing a description of the steps you're taking and the register dump from steps A1 and A7.  I have a few observations based on your register dump.

• How long are you waiting between steps A6/B6 and A7/B7?  Note that CDR lock and adaptation does take some time.  Based on data sheet, for 10.3125 Gbps data, adaptation takes ~74ms.  Note this is a div-1 rate.  For sub-rate data rates, this will take longer.  If you're using div-4 or div-8, 600ms should provide sufficient time for adaptation to complete.
• I noticed that CDR bypass appears to be enabled.  Is this intentional?
• What data rate is the input to the DS125DF410?  I am wondering if the CTLE value in register 0x3A is determining the CTLE value.  The value from this register is used for divider settings >2.  You can enable adaptation for divider settings >2 by setting channel register 0x6F[7]=1.

Thanks,

Drew

Hi Drew-san,

Thank you for reviewing the register dump and providing feedback.
Here are my responses:

- How long are you waiting between steps A6/B6 and A7/B7?

About 1 second. Based on your response, it seems that waiting more than 600ms should be sufficient, so I understand that the wait time in our current debugging environment is adequate.

- CDR bypass appears to be enabled. Is this intentional?

Yes, it is. I understand that CDR is used to separate the clock signal from the data signal that has the clock signal superimposed. In our system, we are inputting a 6.25Gbps signal over 4 lanes to the DS125DF410. The DS125DF410 is used for signal restoration between the Aurora transmission lines of the FPGA used on the transmitting side and the FPGA used on the receiving side.

- What data rate is the input to the DS125DF410?

We are inputting a 6.25Gbps signal over 4 lanes. Since register 0x2F is set to B6, I understand that the divider setting is >2. Based on your response, if I set 0x6F[7] to 1 immediately after (Step A2/Step B2), will the Auto Adaptation CTLE be executed, resulting in a difference in the register values read at (Step A7/B7)?

Hi Tatsumasa-san,

Tatsumasa Imai said:

About 1 second. Based on your response, it seems that waiting more than 600ms should be sufficient, so I understand that the wait time in our current debugging environment is adequate.

Thanks for clarifying.  Yes, I agree this should be sufficient.

Tatsumasa Imai said:

Yes, it is. I understand that CDR is used to separate the clock signal from the data signal that has the clock signal superimposed. In our system, we are inputting a 6.25Gbps signal over 4 lanes to the DS125DF410. The DS125DF410 is used for signal restoration between the Aurora transmission lines of the FPGA used on the transmitting side and the FPGA used on the receiving side.

In general, CDR is used to retime the signal.  There is an internal PLL that helps filter jitter from the input signal in order to create a clean internal recovered clock.  The recovered clock is then used to retransmit the signal with reduced jitter.  This is the typical application of a retimer and is what differentiates a retimer from a redriver.

Based on my understanding of your application, I believe you should be using the retimed signal from the DS125DF410 instead of CDR bypass for improved jitter.  Please let me know if I'm missing something.

Tatsumasa Imai said:

We are inputting a 6.25Gbps signal over 4 lanes. Since register 0x2F is set to B6, I understand that the divider setting is >2. Based on your response, if I set 0x6F[7] to 1 immediately after (Step A2/Step B2), will the Auto Adaptation CTLE be executed, resulting in a difference in the register values read at (Step A7/B7)?

Data at 6.25 Gbps fits into the "div-2" criteria.  However, I'm wondering if it's possible that the retimer is not correctly identifying the rate and is locking to "div-4".  If the retimer is locking to div-4, then by default, the retimer uses the CTLE value in 0x3A.  The reason I'd like to explore this is that from your register dump, the CTLE value observed in register 0x03 is the same value set in 0x3A.  It's not clear to me if this is a coincidence or if 0x80 is actually the best CTLE value.

A couple experiments to try to determine if 0x3A is impacting your observations:

• Change value in 0x3A to a different value and see if this impacts observed CTLE value in 0x03
• Set 0x6F[1] after step A2/B2 and then follow the remaining steps to step A7/B7.

Also, I took a look at the CDR rate setting in 0x60 - 0x63 and was a bit confused.  it looks like your current settings select for VCO rate of 11.88 Gbps.  Would it be possible to share how you selected these values?

Following the data sheet (Section 7.4.4 "Standards-Based Modes"), I arrived at the following values.

Data rate = 12.5 Gbps (6.25 Gbps and div-2)

PPM = 1000

N_PPM = 12.5 * 1280 = 16000

0x60 / 0x62 = (N_PPM & 0xFF)

0x61 / 0x62 = ((N_PPM & 0xFF00) >> 8) | (1 << 7)

Thanks,

Drew

Hi, Drew-san,

I have looked into various aspects of our system.

- **Reason for not using CDR:**

I spoke with someone who was slightly involved in the design of our system. They mentioned that there was an attempt to use CDR in the past, but it didn't work well. The specifics of what "didn't work well" means are unclear, but it seems there were instances where the CDR would occasionally lose lock. Additionally, the CDR performance in the FPGA, which is the output destination of this Retimer IC, is quite good, so it was decided that there was no need to force the use of CDR in the Retimer IC. For these reasons, it was concluded to only use the CTLE Gain addition.

- **Reason for VCO Rate being 11.88GBps:**

I had incorrect information. The signal input to this Retimer IC is actually 5.94Gbps 4Lane.

- **Could register 0x3A be affecting register 0x03?**

I checked using the method you taught me. The specific steps are as follows:
　(step C1) Connect the transmitting device and the receiving device with Cable A (approximately 4m).
　(step C2) Write 0Ch to register 0xFF.
　(step C3) Write 0Ch to register 0x3A. (default: reg 0x3A = 80h)
　(step C4) Write 80h to register 0x6F. (0x6F[7] = 1)
　(step C5) Write 20h to register 0x31.
　(step C6) Write 1Ch to register 0x0A.
　(step C7) Wait for more than 1 sec.
　(step C8) Write 10h to register 0x0A.
　(step C9) Read register 0x03.

As a result, it was confirmed that the value of register 0x03 indeed follows that of 0x3A.
Now, considering the above points, we have a few questions that remain unclear:
　- What register settings are necessary when inputting a 5.94Gbps 4Lane signal?
　- Is the Auto Adaptive CTLE function of the same IC usable even when CDR is turned off?

Regards.