DP83TC812R-Q1: DP83TC812R-Q1 strapping conflict

Hi Vitaliy,

The "OPEN" condition described by the strap tool in the schematic checklist means that neither an independent pullup or an independent pulldown is applied to the pin. I see what you mean by the pin not actually being open-circuited when a LED is attached. The pin has an internal pulldown resistor with a typical value of 8.4k (see page 20 in the datasheet), so my understanding is that if we attached an LED and current limiting resistor outside, the effect would be similar to the left diagram in Figure 7-19 and it should work fine:

I checked the implementation of the LED_0 circuits on the DP83TC812MC-EVM for reference:

The upper circuit is meant for master mode (2.49k pullup on LED_0) and the lower circuit is mean for slave mode (checklist would suggest that LED_0 is open). We see that the EVM implements the slave mode circuit with a 2.49k external pulldown that is the same as the left side of Figure 7-19 but not suggested by the checklist. Since there is already an internal pulldown on the pin, the external pulldown should not really change what the strap is reading at power-up. I will check with my team to see if there is some extra consideration for doing this.

Best,

Evan Su

Thank you for your reply and doing further research on this.  We can also arrange direct call with our company if it's easier. 

To understand correctly, OPEN means there's still internal pull down and it's OK to have external pull down (LED+ resistor) since that doesn't conflict with internal pull down.  

There are also different values for pull downs to consider. Assuming this is related to 3 voltage level config. 

Reason I'm asking is I need to understand also what the IC upstream (MAC) that drives RMII lines need to do with it's outputs (and when timing-wise) upon power up to avoid contention with strap pins (i.e. I assume MAC must have high impedance tristate RMII inputs/outputs upon power up and reset release to allow PHY to properly sample the straps). 

Two follow up questions:

Based on figure 6-7 power up timing, it looks like MAC should keep it's outputs in tristate for at least 10ms upon release of reset.  Could you confirm REF_CLK doesn't need to be running for the phy to sample the straps based on the diagram?

I plan to configure this PHY in the slave mode with MAC driving the clock at X1 and managed mode. In managed mode, can all the configurations be done via registers update (as long as phy reads master/slave and its address straps initially correctly) to bypass strapping issues?

Here's what I'm planning to do with straps using your tool:

Hi Vitaliy,

Vitaliy M said:

Based on figure 6-7 power up timing, it looks like MAC should keep it's outputs in tristate for at least 10ms upon release of reset.  Could you confirm REF_CLK doesn't need to be running for the phy to sample the straps based on the diagram?

I'm checking this internally and will try to get the feedback to you tomorrow.

Vitaliy M said:

I plan to configure this PHY in the slave mode with MAC driving the clock at X1 and managed mode. In managed mode, can all the configurations be done via registers update (as long as phy reads master/slave and its address straps initially correctly) to bypass strapping issues?

All device settings listed in the strap tool can be edited in the register interface. I have personally changed the MAC interface and master/slave configuration through the registers after powerup for example. Strapping the PHY to boot in managed mode could be a workaround if there's a concern about strapping issues. If major changes are to be programmed in the registers compared to what is happening in the straps, it would be good to test it out to make sure no state machines or timings are being thrown off.

Best,

Evan Su