TFP410 not recognizing monitor connection

Hello Joseph,

What is the frequency and amplitude of the signal at IDCK ?

Can you share your schematic?

Do you have a pull-up on MSEN?

Regards.

Elias,

Thanks for the quick response.

IDCK is 108 MHz; amplitude is 0 - 3.3V.

We have a pull-up on MSEN.

The DVI transmitter is on page 3 of the attached schematic.

Joe

Hello Joe,

Connect IDCK- to ground.

I see you are using a FPGA to generate the video, can you send a scope capture of the IDCK, DE, HSYNC and VSYNC.

Regards.

Elias,

IDCK- is being driven low by the FPGA; is that good enough?

I'm afraid I can't do a scope capture for you. The DE, HSYNC, and VSYNC signals are being generated by Altera's Clocked Output Buffer Video IP module. All are active high, and look good on the scope. We were able to successfully drive various monitors using this code on an Altera dev kit board going through Bitec's DVI daughterboard for the dev kit.

Joe

Elias, I am also interested in this thread. I have the problems and nearly same schematic. Here is a timing trace from xilinx/sysgen showing hsync, vsync and DE top to bottom:

1018.timing.pdf

Schematic is here, pin 34->gnd as well.

And the overall timing is according to EIA standards:

8865.EIA.pdf

Thanks for any help, I am stuck. Not toggle on msen or any LVDS lines.

Joseph,

Does your DVI receiver installed on your panel implements 3.3-V terminations on the TMDS lines?

Regards.

Elias,

Here's another piece of information for you. I meant to post this earlier, but we've got a ton of stuff on our plates at the moment...

The TXC- pin is outputting a clock signal that is about 1V peak-to-peak with a maximum voltage of 3.3V.

The TXC+ pin is outputting a clock signal that is about 300-400mV peak-to-peak and centered at 0V.

Joe

I was wondering why the clock output would be on the TXC- line.

I'm glad you figured out.

Regards.