SN65DSI86: Question about SN65DSI86

Jimmy Huang

Genius 3515 points

Part Number: SN65DSI86

Tool/software:

Hello：

My customer uses SN65DSI86 for his project，

Problem description: High probability of occurrence, the power key cannot light up the screen

Phenomenon: Press the power button to turn on the screen, and the backlight will light up before the display. There is a low probability of the problem where only the backlight will light up and not display

Device information

Screen: N402-CM2001-000 T603AB/14 inch FHD/INX/HX8052-A01/Panda/KD/National Display

Transfer IC: SN65DSI86

Screen FAE confirmation: If the 3.3V power supply of the screen is normal, the screen can work normally. The screen power supply is provided by LDO, and the actual measurement shows that the screen power supply is normal

Current question:

according to SN65DSI86: LOSS_OF_DP_SYNC_LOCK_ERR - Interface forum - Interface - TI E2E support forums The debug method in the post introduces VSYNC and HSYNC. The measured frequency of HSYNC is 73.6kHz, and there is no change in frequency between normal display and abnormal non display.

SN65DSI86: LOSS_OF_DP_SYNC_LOCK_ERR - Interface forum - Interface - TI E2E support forums

Please help confirm the following questions:

1、How to determine the problem point after measuring the HSYNC frequency?

2、What other configurations need to be checked for problem point confirmation when 0xF6=0x40?

25 days ago

0 Ikram Haque 24 days ago

TI__Mastermind 22830 points

Hi Jimmy,

1. From the Sync frequency is the pulse count and pulse length matching the display resolution timings? Could you please share the programmed timings so we can confirm it matches the measurement.

2. Is it confirmed that this is the only error occurring? What do registers 0xF0 - 0xF8 show?

DP sync errors could be related to a timing mismatch between what is programmed from the SoC (source) and the timings programmed on the DSI86. Since this is high probability, this could imply there is some correction needed for programming or other timing implementation.

Best regards,
Ikram

0 ? ?? 23 days ago in reply to Ikram Haque

Prodigy 30 points

Hi,

1.timmings as bellow

panel proch

2.bellow is F0~F8's value

abnorml state

Normal brightness

0 Ikram Haque 22 days ago in reply to ? ??

TI__Mastermind 22830 points

Hello,

1. After initialization, please include a step to write 0xFF to registers 0xF0 - 0xF8 to clear the error checking registers. Then read the registers in working and not working conditions.

2. It seems that one of the differences is the 0xF6 register shows LOSS_OF_DP_SYNC_LOCK_ERR when the issue occurs. Is the DSI clock programmed timing matching the pixel clock rate? What is the DSI clock rate set to?

I will also check the timings shared and the DSI86 register settings to get back to you in 1-2 days.

Best regards,
Ikram