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DS110DF410: Regarding Read/Write Operations to the Control/Shared Registers and Channel Registers of DS110DF410SQ

Part Number: DS110DF410
Other Parts Discussed in Thread: DS100DF410

Tool/software:

Hello,

We are currently verifying the Read/Write behavior of each register of the DS110DF410SQ via SMBus.
We have several questions and would appreciate your clarification.

(1) My understanding is that the Control/Shared Register at address 0xFF (Channel Select Register) cannot be read via SMBus.
Therefore, I believe it is not possible to confirm whether the correct value has been written to address 0xFF by reading it back and checking for consistency.
Is this understanding correct?
Also, if there is a method to confirm whether the correct value has been written to address 0xFF, please let us know.

(2) My understanding is that when writing 0x04 to the Channel Register at address 0x00, all channel registers are restored to their default values.
Therefore, immediately after doing so, if the value of the Channel Register at address 0x00 is read again, the default value of 0x00 will be read out instead of 0x04.
Is this understanding correct?
  

(3) My understanding is that all 0-7 bits of the Channel Register at address 0x3F are reserved.
If a value is written to this register, will it be correctly stored?
Also, when reading it back, will the value written be returned?
Please clarify the expected behavior of Read/Write operations on registers where all bits are reserved.

(4) After writing 0x04 to the Channel Register at address 0x00 (restoring all channel registers to their default values), we found that reading from address 0x03 returned 0xA5.
We expected the default value 0x00 to be returned, but this was not the case.
Could you advise us on possible reasons for this behavior?


Best regards,

K.Hirano

  • Hi Hirano-san,

    1. The digital behavior on the DS100DF410 is a bit strange, and register 0xFF will read back 0xA5 every time.  What seems to happen is that while a channel register set is selected, outside of the typical channel register range (0x00-0x75), registers will read back values from 0x40-0x5F.  Setting register 0xFF on 10G retimers is one of the few cases were I would not recommend a RMW procedure.

    Please also see this e2e

     DS110DF410: Reg 0xFF programming issue. 

    2. Yes, your understanding is correct.

    3. What is your interest in writing to register 0x3F?  We would expect it to store values written to it, although in many cases, reserved registers are internal registers and altering these may have unintended effects.

    4. In this case, is the retimer provided an input signal?  I'm curious if the register value could be changing due to adaptation.

    Thanks,

    Drew

  • Drew,

    Thank you for your prompt response.

    1.
    They understand that RMW (Read-Modify-Write) operations for register 0xFF are not recommended.

    2.
    Understood.

    3.
    They asked about writing to register 0x3F because of a request from the customer.
    However, since it is possible that this was a mistake on the customer's side, they will confirm this with the customer.
    Anyway they understood your response regarding this matter.

    4.
    They will check whether an input signal is being supplied to the retimer and get back to you.
    Additionally, they wrote 0x00 to register 0x03 via SMBus and was able to read back 0x00 as expected.
    The customer requested that 0x00 be written to register 0x03 at startup.
    By reading back the value after writing, they would like to confirm whether the write was successful.
    Is this OK or not recommended?

    Best Regards,

    K.Hirano

  • Hi Hirano-san,

    4. The customer can write 0x00 to register 0x03.  Note that this register reflects the CTLE value and will be changed by the retimer adaptation.  I'd recommend reviewing section 8.5.8, "Overriding the CTLE Boost Setting", section of the data sheet.

    Thanks,
    Drew

  • Dear Drew

    Thank you very much for your response.

    We have understood that it is possible to write 0x00 to address 0x03. We also understand that the value written may change due to the retimer’s adaptation. Our customer has requested us to configure the retimer as follows (settings are applied in order from top to bottom):


    In our design, immediately after writing to each register, we perform a read operation to confirm whether the written value can be read back as is, in order to verify that the write operation was successful. As you advised previously, reading from register 0xFF is not recommended, so we are skipping the read-back check for 0xFF. Additionally, when writing 0x04 to register 0x00, if the read-back value is 0x00 (the default value), we consider this to be acceptable.

    (Q1) When we write 0x00 to register 0x03 and immediately read back the value of register 0x03, can you guarantee that 0x00 will be read back?
    If there is a possibility that the retimer’s adaptation may change it to a value other than 0x00, we think that the read-back check for register 0x03 should be skipped, just as we do for register 0xFF.

    (Q2) Regarding the registers to which we are writing, if there are any other registers besides 0xFF for which the read-back check should be skipped, please let us know.

    We would appreciate your advice on this matter.

    Best Regards,
    Tetsuya Masuda

  • Hi Masuda-san,

    Can you share some detail on why the customer is enabling raw data?  It is a bit surprising to select a retimer device and enable raw data.

    1. Once adapt mode is set to 0, we do not expect retimer adaptation to change the value in register 0x03.

    2. Besides registers 0x00 and 0xFF, you should be able to perform read-back check on the other registers.

    Thanks,

    Drew

  • Dear Drew

    Thank you for your response.

    1. I understand that if the adapt mode is set to 0 (writing 0x00 to register 0x31), it is possible to perform a read-back check when writing 0x00 to register 0x03.

    2. Understood.


    I have an additional question. Regarding your comment, "It is a bit surprising to select a retimer device and enable raw data," do you mean that setting raw data (setting 0x00 for EQ boost) would make using the retimer device meaningless? Is my understanding correct?

  • Hi Masuda-san,

    The customer appears to be following the "raw mode" sequence from the programming guide.

    One of the key features of a retimer device is the CDR circuit.  This allows for the device to filter out jitter from the input signal and output a "clean" signal.  Since there is an internal recovered clock, this also enables more advanced equalization like DFE.

    In raw mode, the customer is bypassing the CDR circuit, so the output signal is not retimed.  In this mode, the retimer acts more like a redriver.

    Thanks,

    Drew

  • Dear Drew,

    Thank you for providing the programming guide.
    I also appreciate your detailed explanation. I have understood the content.

    I will check with the customer regarding the intention behind setting the raw mode on the retimer, or whether there might be any mistake in their request.


    Thank you for your support.

    Best Regards,
    Tetsuya Masuda